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参数资料
| 型号： | LIS33DE |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PBGA16 |
| 封装： | 3 X 3 MM, 1 MM HEIGHT, GREEN, PLASTIC, LGA-16 |
| 文件页数： | 9/31页 |
| 文件大小： | 532K |
| 代理商： | LIS33DE |
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LIS33DE
Digital interfaces
Doc ID 15596 Rev 1
17/31
5.1.1
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the Master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the Master.
The Slave ADdress (SAD) associated to the LIS33DE is 001110xb. SDO pad can be used to
modify less significant bit of the device address. If SDO pad is connected to voltage supply
LSb is ‘1’ (address 0011101b) else if SDO pad is connected to ground LSb value is ‘0’
(address 0011100b). This solution permits to connect and address two different
accelerometers to the same I2C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data has
been received.
The I2C embedded inside the LIS33DE behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, a 8-bit sub-address is transmitted: the 7 LSb
represent the actual register address while the MSB enables address auto increment. If the
MSb of the SUB field is 1, the SUB (register address) is automatically incremented to allow
multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition is issued after the two sub-address bytes; if the bit is ‘0’ (Write) the
Master will transmit to the slave with direction unchanged.
Table 10.
Transfer when Master is writing one byte to slave
Table 11.
Transfer when Master is writing multiple bytes to slave:
Table 12.
Transfer when Master is receiving (reading) one byte of data from slave:
Master
ST
SAD + W
SUB
DATA
SP
Slave
SAK
Master
ST
SAD + W
SUB
DATA
SP
Slave
SAK
Master
ST
SAD + W
SUB
SR
SAD + R
NMAK
SP
Slave
SAK
DATA
Table 13.
Transfer when Master is receiving (reading) one byte of data from slave
Master
ST
SAD + W
SUB
SR
SAD + R
NMAK
SP
Slave
SAK
DATA
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