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参数资料
| 型号： | LM12434CIWMX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封装： | SOP-28 |
| 文件页数： | 18/80页 |
| 文件大小： | 1552K |
| 代理商： | LM12434CIWMX |
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60 Operational Information
61 FUNCTIONAL DESCRIPTION
The LM12434 and LM12 L 438 are multi-functional Data
Acquisition Systems that include a fully differential 12-bit-
plus-sign self-calibrating analog-to-digital converter (ADC)
with a two’s-complement output format
an 8-channel
(LM12 L 438) or a 4-channel (LM12434) analog multiplex-
er a first-in-first-out (FIFO) register that can store 32 con-
version results and an Instruction RAM that can store as
many as eight instructions to be sequentially executed The
LM12434 also has a differential multiplexer output and a
differential SH input All of this circuitry operates on only a
single a5V power supply For simplicity the DAS (Data Ac-
quisition System) abbreviation is used as a generic name for
the members of the LM12434 and LM12 L 438 family
thoughout this discussion
Figure 7 illustrates the functional block diagram or user pro-
gramming model of the DAS Note that this diagram is not
meant to reflect the actual implementation of the internal
building blocks The model consists of the following blocks
A flexible analog multiplexer with differential output at
the front end of the device
A fully-differential self-calibrating 12-bit a sign ADC
converter with sample and hold
A 32-word FIFO register as the output data buffer
An 8-word instruction RAM that can be programmed to
repeatedly perform a series of conversions and compari-
sons on selected input channels
A series of registers for overall control and configuration
of DAS operation and indication of internal operational
status
Interrupt generation logic to request service from the
processor under specified conditions
Serial interface logic for inputoutput operations be-
tween the DAS and the processor All the registers
shown in the diagram can be read and most of them can
also be written to by the user through the inputoutput
block
A controller unit that manages the interactions of the
different blocks inside the DAS and controls the conver-
sion comparison and calibration sequences
The DAS has 3 different modes of operation
12-bit a sign conversion
8-bit a sign conversion
8-bit a sign comparison (also called ‘‘watchdog’’ mode)
The fully differential 12-bit-plus-sign ADC uses a charge re-
distribution topology that includes calibration capabilities
Charge re-distribution ADCs use a capacitor ladder in place
of a resistor ladder to form an internal DAC The DAC is
used by a successive approximation register to generate
intermediate voltages between the voltages applied to
VREFb and VREFa These intermediate voltages are com-
pared against the sampled analog input voltage as each bit
is charged
Conversion accuracy is ensured by an internal auto-calibra-
tion system Two different calibration modes are available
one compensates for offset voltage or zero error while the
other corrects the ADC’s linearity and offset errors
When correcting offset only the offset error is measured
once and a correction coefficient is created During the full
calibration the offset error is measured eight times aver-
aged and a correction coefficient is created After comple-
tion of either calibration mode the offset correction coeffi-
cient is stored in an internal offset correction register
The LM12434 and LM12 L 438’s overall linearity correction
is achieved by correcting the internal DAC’s capacitor mis-
match Each capacitor is compared eight times against all
remaining smaller value capacitors and any errors are aver-
aged A correction coefficient is then created and stored in
one of the thirteen linearity correction registers A state ma-
chine using patterns stored in 16-bit x 8-bit ROM executes
each calibration algorithm
Once the converter has been calibrated an arithmetic logic
unit (ALU) uses the offset correction coefficient and the 13
linearity correction coefficients to reduce the conversion’s
offset error and linearity error in the background during the
12-bit a sign conversion 8-bit a sign conversions and
‘‘watchdog’’ comparisons use only the offset coefficient An
8-bit a sign conversion requires less than half the time
needed for a 12-bit a sign conversion
Diagnostic Mode
A diagnostic mode is available that allows verification of the
LM12 L 438’s operation The diagnostic mode is disabled
in the LM12434 This mode internally connects the voltages
present at the VREFa and VREFb pins to the internal VINa
and VINb SH inputs This mode is activated by setting the
Diagnostic bit (Bit 11) in the Configuration register to a ‘‘1’’
More information concerning this mode of operation can be
found in Section 622
Watchdog Mode
In the watchdog mode no conversion is performed but the
DAS samples an input and compares it with the values of
the two limits stored in the Instruction RAM If the input
voltage is above or below the limits (as defined by the user)
an interrupt can be generated to indicate a fault condition
The LM12434 and LM L 438’s ‘‘watchdog’’ mode is used
to monitor a single-ended or differential signal’s amplitude
and generate an output if the signal’s amplitude falls out-
sidde of a programmable ’‘window’’ Each watchdog instruc-
tion includes two limits An interrupt can be generated if the
input signal is above or below either of the two limits This
allows interrupt to be generated when analog voltage inputs
are ‘‘outside the window’’ After a ‘‘watchdog’’ mode inter-
rupt the processor can then request a conversion on the
input signal and read the signal’s magnitude
Analog Input Multiplexer
The analog input multiplexer can be configured for any com-
bination of single-ended or fully differential operation Each
input is referenced to AGND when a multiplexer channel
operates in the single-ended mode Fully differential analog
input channels are formed by pairing any two channels to-
gether
The LM12434’s multiplexer outputs and SH inputs
(MUXOUTa MUXOUTb and SH INa SH INb) provide
the option for additional analog signal processing after the
multiplexer Fixed-gain amplifiers programmable-gain am-
plifiers filters and other processing circuits can operate on
the multiplexer output signals before they are applied to the
ADC’s SH inputs If external processing is not used con-
nect MUXOUTa to SH INa and MUXOUTb to SH INb
25
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相关代理商/技术参数 |
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|---|---|
| LM12438CIV | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Sign Data Acquisition System with Serial I/O and Self-Calibration |
| LM12438CIWM | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Sign Data Acquisition System with Serial I/O and Self-Calibration |
| LM12454 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:General Purpose Controller Z84C15 |
| LM12454_06 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:12-Bit + Sign Data Acquisition System with Self-Calibration |
| LM12454A WAF | 制造商:Texas Instruments 功能描述: |
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