- 您现在的位置：买卖IC网 > PDF目录44529 > LM12458CIVF/NOPB (NATIONAL SEMICONDUCTOR CORP) SPECIALTY ANALOG CIRCUIT, PQFP44 PDF资料下载
参数资料
| 型号： | LM12458CIVF/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP44 |
| 封装： | PLASTIC, QFP-44 |
| 文件页数： | 24/36页 |
| 文件大小： | 1195K |
| 代理商： | LM12458CIVF/NOPB |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页当前第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
3.0 Other Registers and Functions
(Continued)
ceeds the threshold stored in the instruction’s Limit #1 reg-
ister. When, for example, instruction 3 is a “watchdog” op-
eration (Bit 11 is set high) and the input for instruction 3
meets the magnitude and/or polarity data stored in instruc-
tion 3’s Limit #1 register, Bit 3 in the Limit Status register will
be set to a “1”.
Bits 8–15 show the Limit #2 status. Each bit will be set high
(“1”) when the corresponding instruction’s input voltage ex-
ceeds the threshold stored in the instruction’s Limit #2 reg-
ister. When, for example, the input to instruction 6 meets the
value stored in instruction 6’s Limit #2 register, Bit 14 in the
Limit Status register will be set to a “1”.
3.3 TIMER
The LM12(H)454/8 have an on-board 16-bit timer that in-
cludes a 5-bit pre-scaler. It uses the clock signal applied to
pin 23 as its input. It can generate time intervals of 0 through
2
21 clock cycles in steps of 25. This time interval can be used
to delay the execution of instructions. It can also be used to
slow the conversion rate when converting slowly changing
signals. This can reduce the amount of redundant data
stored in the FIFO and retrieved by the controller.
The user-defined timing value used by the Timer is stored in
the 16-bit READ/WRITE Timer register at location 1011
(A4–A1, BW = 0) or 1011x (A4–A0, BW = 1) and is pre-
loaded automatically. Bits 0–7 hold the preset value’s low
byte and Bits 8–15 hold the high byte. The Timer is activated
by the Sequencer only if the current instruction’s Bit 9 is set
(“1”). If the equivalent decimal value “N” (0
≤ N ≤ 216 1)is
written inside the 16-bit Timer register and the Timer is
enabled by setting an instruction’s bit 9 to a “1”, the Se-
quencer will delay the same instruction’s execution by halt-
ing at state 3 (S3), as shown in Figure 15, for 32 x N + 2
clock cycles.
3.4 DMA
The DMA works in tandem with Interrupt 2. An active DMA
Request on pin 32 (DMARQ) requires that the FIFO interrupt
be enabled. The voltage on the DMARQ pin goes high when
the number of conversions in the FIFO equals the 5-bit value
stored in the Interrupt Enable register (bits 11–15). The
voltage on the INT pin goes low at the same time as the
voltage on the DMARQ pin goes high. The voltage on the
DMARQ pin goes low when the FIFO is emptied. The Inter-
rupt Status register must be read to clear the FIFO interrupt
flag in order to enable the next DMA request.
DMA operation is optimized through the use of the 16-bit
data bus connection (a logic “0” applied to the BW pin).
Using this bus width allows DMA controllers that have single
address Read/Write capability to easily unload the FIFO.
Using DMA on an 8-bit data bus is more difficult. Two read
operations (low byte, high byte) are needed to retrieve each
conversion result from the FIFO. Therefore, the DMA con-
troller must be able to repeatedly access two constant ad-
dresses when transferring data from the LM12(H)454/8 to
the host system.
4.0 FIFO
The result of each conversion stored in an internal read-only
FIFO (First-In, First-Out) register. It is located at 1100
(A4–A1, BW = 0) or 1100x (A4–A0, BW = 1). This register
has 32 16-bit wide locations. Each location holds 13-bit data.
Bits 0–3 hold the four LSB’s in the 12 bits + sign mode or
“1110” in the 8 bits + sign mode. Bits 4–11 hold the eight
MSB’s and Bit 12 holds the sign bit. Bits 13–15 can hold
either the sign bit, extending the register’s two’s complement
data format to a full sixteen bits or the instruction address
that generated the conversion and the resulting data. These
modes are selected according to the logic state of the Con-
figuration register’s Bit 5.
The FIFO status should be read in the Interrupt Status
register (Bits 11–15) to determine the number of conversion
results that are held in the FIFO before retrieving them. This
will help prevent conversion data corruption that may take
place if the number of reads are greater than the number of
conversion results contained in the FIFO. Trying to read the
FIFO when it is empty may corrupt new data being written
into the FIFO. Writing more than 32 conversion data into the
FIFO by the ADC results in loss of the first conversion data.
Therefore, to prevent data loss, it is recommended that the
LM12(H)454/8’s interrupt capability be used to inform the
system controller that the FIFO is full.
The lower portion (A0 = 0) of the data word (Bits 0–7) should
be read first followed by a read of the upper portion (A0 = 1)
when using the 8-bit bus width (BW = 1). Reading the upper
portion first causes the data to shift down, which results in
loss of the lower byte.
Bits 0–12 hold 12-bit + sign conversion data. Bits 0–3 will
be 1110 (LSB) when using 8-bit plus sign resolution.
Bits 13–15 hold either the instruction responsible for the
associated conversion data or the sign bit. Either mode is
selected with Bit 5 in the Configuration register.
Using the FIFO’s full depth is achieved as follows. Set the
value of the Interrupt Enable register’s Bits 11–15 to 11111
and the Interrupt Enable register’s Bit 2 to a “1”. This gener-
ates an external interrupt when the 31st conversion is stored
in the FIFO. This gives the host processor a chance to send
a “0” to the LM12(H)454/8’s Start bit (Configuration register)
and halt the ADC before it completes the 32nd conversion.
The Sequencer halts after the current (32) conversion is
completed. The conversion data is then transferred to the
FIFO and occupies the 32nd location. FIFO overflow is
avoided if the Sequencer is halted before the start of the
32nd conversion by placing a “0” in the Start bit (Configura-
tion register). It is important to remember that the Sequencer
continues to operate even if a FIFO interrupt (INT 2) is
internally or externally generated. The only mechanisms
that stop the Sequencer are an instruction with the PAUSE
bit set to “1” (halts before instruction execution), placing a “0”
in the Configuration register’s START bit, or placing a “1” in
the Configuration register’s RESET bit.
5.0 Sequencer
The Sequencer uses a 3-bit counter (Instruction Pointer, or
IP, in Figure 9) to retrieve the programmable conversion
instructions stored in the Instruction RAM. The 3-bit counter
is reset to 000 during chip reset or if the current executed
instruction has its Loop bit (Bit 1 in any Instruction RAM “00”)
set high (“1”). It increments at the end of the currently
executed instruction and points to the next instruction. It will
continue to increment up to 111 unless an instruction’s Loop
bit is set. If this bit is set, the counter resets to “000” and
execution begins again with the first instruction. If all instruc-
tions have their Loop bit reset to “0”, the Sequencer will
execute all eight instructions continuously. Therefore, it is
important to realize that if less than eight instructions are
programmed, the Loop bit on the last instruction must be set.
LM12454/LM12458/LM12H458
www.national.com
30
相关PDF资料 |
PDF描述 |
|---|---|
| LM129AGMW8 | 1-OUTPUT TWO TERM VOLTAGE REFERENCE, 6.9 V, UUC |
| LM12H458MW/883 | SPECIALTY ANALOG CIRCUIT, CQFP44 |
| 5962-9319502MXC | SPECIALTY ANALOG CIRCUIT, CQCC44 |
| LM12L454CIV | SPECIALTY ANALOG CIRCUIT, PQCC44 |
| LM134MWC | SPECIALTY ANALOG CIRCUIT, UUC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LM12458CIVX | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| LM12458CIVX/NOPB | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| LM12458CMEL/883 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Single-Ended Data Acquisition System |
| LM12458MEL/883 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Single-Ended Data Acquisition System |
| LM12458MW/883 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Single-Ended Data Acquisition System |
发布紧急采购，3分钟左右您将得到回复。