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参数资料
| 型号： | LM2637M/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO24 |
| 封装： | SOIC-24 |
| 文件页数： | 5/17页 |
| 文件大小： | 803K |
| 代理商： | LM2637M/NOPB |
Applications Information (Continued)
Linear Section — The linear section is designed for high
control bandwidth operation. The phase margin and cutoff
frequency depends on the external N-FET, output capacitors
and their ESR. As a rule of thumb, the designer can choose
any capacitance from 50 F to 4000 F, with a total ESR of
10 m
to 100 m. The larger the capacitance, the lower the
bandwidth. The above capacitors usually result in a control
bandwidth of 250 kHz to 1.2 MHz.
FET Selection
Switching Section — The selection of FET switches affects
both the efficiency of the whole converter and the current
limit setting (if V
DS sensing mode is selected). From effi-
ciency standpoint it is suggested that for the high-side
switch, only logic level FETs be used. Standard FETs can be
used for the low-side switch when 12V is used to power the
V
DD pin. The power loss associated with the FETs is two-
fold — Ohmic loss and switching loss. The Ohmic loss is
relatively easy to calculate whereas the switching loss is
much more difficult to estimate. The switching loss in a
synchronous buck converter usually happens only in the
high-side FET. When the high-side FET starts to turn on,
inductor current is flowing in the low-side body diode. Since
the body diode undergoes a reverse recovery before forced
off, the high-side FET will experience a pulse of drain current
turn on. The simultaneous presence of high drain-source
voltage and high drain current in the high-side FET causes
the switching loss. Apparently the switching loss is propor-
tional to the PWM frequency. Having a Schottky diode in
parallel with the low-side body diode will to a large extent
alleviate the problem. This is because a Schottky diode does
not undergo a reverse recovery and it has a lower forward
voltage than the body diode so it will take the majority of the
inductor current after the low-side FET is turned off. The
low-side FET benefits from what is called zero voltage
switching (ZVS). That is because every time just before the
low-side FET is turned on, inductor current is already flowing
in its body diode, resulting in a low drain-source voltage.
When the low-side FET is turned off, current will be shifted to
its body diode temporarily, again clamping the drain-source
voltage to a low value.
It is difficult to calculate the switching loss due to its compli-
cated nature. Fortunately at a reasonable PWM frequency
such as 300 kHz, the switching loss is usually much less
than the Ohmic loss. So the designer may initially ignore the
switching loss when trying to meet an efficiency specifica-
tion.
The Ohmic loss for the high-side FET is:
(12)
The Ohmic loss for the low-side FET is:
(13)
Notice when determining the r
DS_ON, the gate-source volt-
ages are usually different for the two FET’s. For the high-side
FET, V
GS is VDD minus drain voltage. For the low-side, VGS
is V
DD. This means the low-side FET may present a lower
r
DS_ON when the same type of FET is used for both switches.
Since the r
DS_ON has a positive temperature coefficient, the
actual Ohmic loss may be somewhat higher than calculated.
The power supply designer may target 125C FET operating
temperature under maximum load and highest ambient tem-
perature and then use the corresponding r
DS_ON found in the
FET datasheet.
Linear Section — Two things need to be considered, i.e.,
r
DS_ON and thermal capacity. Make sure that the maximum
possible r
DS_ON on the N-FET is lower than the lowest
input-output differential voltage divided by maximum load
current. In a typical motherboard 3.3V to 1.5V or 3.3V to
2.5V application, this is not an issue because the maximum
allowable r
DS_ON is way higher than a typical N-FET. It is the
thermal capacity and cost that limits the selection. As an
example, consider a 3.3V to 1.5V, 4A application. The lowest
input-output differential voltage is 3.3V x 95% –1.5V x 102%
= 1.605V, so the maximum allowable r
DS_ON is 1.605V ÷ 4A
= 401 m
. Almost all low voltage discrete N-FET’s can meet
this requirement. However, the maximum power dissipation
on the FET is (3.3V x 105% –1.5V x 98%) x 4A = 8W. At least
a TO-220 package with a beefy heat sink is necessary to
handle the thermal dissipation. When there is a load tran-
sient requirement such as that of the GTL+ supply, make
sure the r
DS_ON is much lower than the value calculated from
steady state operation because headroom is important for
transient performance.
Capacitor Selection
Switching Section —
Output Capacitors. The selection of capacitors is an ex-
tremely important step when designing a converter for a load
such as the MPU core. Since the typical slew rate of the load
current during a large load transient is around 20 A/s to 30
A/s, the switching converter has to rely on the output ca-
pacitors to take care of the first few microseconds. Under
such a current slew rate, ESR of the output capacitors is
more of a concern than the ESL in terms of voltage excur-
sion. Depending on the kind of capacitors being used, total
output capacitance value may or may not be an important
factor. When the output capacitance is too low, the converter
10084819
FIGURE 8. Loop Bode Plots
LM2637
www.national.com
13
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