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参数资料
| 型号： | LM2645MTD/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 335 kHz SWITCHING FREQ-MAX, PDSO48 |
| 封装： | TSSOP-48 |
| 文件页数： | 12/20页 |
| 文件大小： | 911K |
| 代理商： | LM2645MTD/NOPB |
Connection Diagram
TOP VIEW
20015901
48-Lead TSSOP (MTD)
Order Number LM2645MTD
See NS Package Number MTD48
Pin Descriptions
VO1 (Pin 1):The feedback input for Channel 1. Always con-
nect directly to the output. Fixed or adjustable output voltage
is selected by FB1_FIX.
FB1_FIX (Pin 2): The feedback input for setting the output
voltage of Channel 1. Connecting this pin to VLIN5 sets the
output voltage to 5V, or to the center of a voltage divider for
an adjustable output.
COMP1 (Pin 3): Compensation pin for Channel 1. This is the
output of the internal transconductance amplifier. The com-
pensation network should be connected between this pin
and the signal ground, SGND.
LDODRV (Pin 4): The output of the adjustable linear regu-
lator controller. Connects to the base of a PNP Pass transis-
tor. This pin is activated when Channel 1 is enabled.
NC (Pins 5, 9, 20): No internal connection. Connect these
pins to ground.
LDOFB (Pin 6): Dual function input pin. When connected to
the center of a resistor divider, it serves as the 1.238V
feedback input for the LDODRV. Connecting this pin to
VLIN5 disables the LDODRV.
FPWM/2NDFB (Pin 7): Multi-function input pin. When held
HIGH (>2V), pulse-skipping mode is enabled for both
switching regulators. When held LOW (<0.8V), both regula-
tors will function in Fixed Frequency PWM mode. This pin
can also be connected to the center of a resistor divider for
feedback regulation of a secondary winding voltage. In this
case, Ch 1 will operate in pulse-skipping mode when the
output is lightly loaded. If the linear regulator controller out-
put is heavy loaded, the operating frequency in pulse-
skipping will be increased accordingly to maintain the volt-
age at this pin to 1.5V or higher. Thus, the secondary
winding voltage will always have the necessary overhead
voltage for the linear regulator to maintain regulation.
TEST (Pin 8): Special purpose input pin for factory use only.
This pin must be connected to ground.
UV_DELAY (Pin 10): : A capacitor from this pin to ground
adjusts the delay of the undervoltage protection for the two
switching outputs and the linear regulated output controlled
by the LDODRV. The delay time is set by charging a capaci-
tor to 2.3V from a 5A current source. Pulling this pin to
ground disables undervoltage protection on these outputs.
SGND (Pin 11,12): Ground connection for the signal level
circuitry. It should be connected to the ground rail of the
system.
PGOOD1 (Pin 13): An open-drain power-good output for
Channel 1. It is ’LOW’ (low impedance to ground) whenever
the output voltage travels out of the ±10% window. It stays
latched in a ’LOW’ state if the output travels beyond the
positive limit that trips the over-volatge protection.
PGOOD2 (Pin 14): An open drain power good output for
Channel 2. It serves the same function as the PGOOD1.
FSEL (Pin 15): Selects the Switching Frequency of the two
switching controllers. The frequency is 300kHz when this pin
is pulled HIGH (>2V), or 200kHz when this pin is pulled
LOW (<0.8V).
SD (Pin 16): Shutdown control input. Pulling this pin LOW
(<0.6V) turns OFF the entire chip which then draws less
than 10 A of supply current. The chip is ON if this pin is held
HIGH (>2V). Toggling this pin from HIGH to LOW and then
HIGH again resets the chip causing it to recover from any
protection latch.
ON1 (Pin 17): Output enable for Channel 1 and LDODRV
(Pin 4). Channel 1 and LDODRV are disabled when this pin
is pulled LOW (<0.8V), and are enabled when this pin is
pulled HIGH (>2V).
ON2 (Pin 18): Output enable for Channel 2. Channel 2 is
enabled when this pin is pulled high (> 2V) and disabled
when this is pulled low (<0.8V).
SS1 (Pin 19): Soft-start input pin for Channel 1. The rise
time of the output voltage of Channel 1 is programmed by
the charge rate of a capacitor connected from this pin to
ground by an internal 2 A current source. If the output does
not reach regulation (to within 6% of nominal voltage) by
the time this pin exceeds 2V (typical), the UV_DELAY pin
begins charging the capacitor connected from it to ground. If
the output is not within regulation after the UVP delay, the
chip latches off.
SS2 (Pin 21): Soft-start input pin for Channel 2. Serves the
same function as the SS1, Pin 19.
COMP2 (Pin 22): Compensation pin for Channel 2. This is
the output of the internal transconductance amplifier. The
compensation network should be connected between this
pin and the signal ground SGND (Pins 11, 12).
FB2_FIX (Pin 23): The feedback input for setting the output
voltage of Channel 2. Connecting this pin to VLIN5 sets the
output voltage to 3.3V, or to the center of a voltage divider for
an adjustable output.
VO2 (Pin 24): The feedback input for Channel 2. Always
connect directly to the output. Fixed or adjustable output
voltage is selected by FB2_FIX.
ILIM2 (Pin 25): Current limit threshold setting for Channel 2.
It sinks a constant current of 10 A that is converted to a
voltage through a resistor connected from this pin to Vin. The
voltage across this resistor is compared with either the Vds
LM2645
www.national.com
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