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参数资料
| 型号： | LM2645MTD/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 335 kHz SWITCHING FREQ-MAX, PDSO48 |
| 封装： | TSSOP-48 |
| 文件页数： | 3/20页 |
| 文件大小： | 911K |
| 代理商： | LM2645MTD/NOPB |
Electrical Characteristics (Continued)
Unless otherwise specified, V
IN = 15V, SGND = PGND = 0V, VLIN5 = VDD1 = VDD2. Limits appearing in boldface type apply
over the entire operating junction temperature range, 0C to +125C. Specifications appearing in plain type are measured using
low duty cycle pulse testing with T
A = 25C (Note 5), (Note 6). Min/Max limits are guaranteed by design, test, or statistical
analysis.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SYSTEM
I
IL
Maximum Input Leakage
Current (SD,
FPWM/2NDFB, ON1,
ON2, FSEL).
Logic Input Voltage 0 or 5V
±0.1
A
Logic Outputs
I
OL
PGOOD Low Sink
Current
V
PGOOD = 0.4V
1.4
mA
I
OH
PGOOD High Leakage
Current
V
PGOOD =5V
50
200
nA
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is guaranteed. For guaranteed performance limits and associated test conditions, see the Electrical Characteristic tables.
Note 2: Maximum allowable power dissipation is calculated by using PDMAX =(TJMAX -TA)/θJA, where TJMAX is the maximum junction temperature, TA is the
ambient temperature and
θJA is the junction-to-ambient thermal resistance of the specified package. The 1.56W rating results from using 150C, 25C, and 80C/W
for TJMAX,TA, and θJA respectively. A θJA of 90C/W represents the worst-case condition of no heat sinking of the 48-pin TSSOP. Heat sinking allows the safe
dissipation of more power. The Absolute Maximum power dissipation should be derated by 12.5mW per C above 25C ambient. The LM2645 actively limits its
junction temperature to about 150C.
Note 3: For detailed information on soldering plastic small-outline packages, refer to the Packaging Databook available from National Semiconductor Corporation.
Note 4: Except for SW1, SW2, CBOOT1 and CBOOT2 pins which are 1.5kV. For testing purposes, ESD was applied using the human-body model, a 100pF
capacitor discharged through a 1.5k
resistor.
Note 5: A typical is the center of characterization data measured with low duty cycle pulse tsting at TA = 25C. Typicals are not guaranteed.
Note 6: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TA =TJ = 25C. All hot and cold limits
are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
Note 7: Both switching controllers are OFF. The linear regulators VLIN5 and 3OUT remain ON.
Note 8: The output voltage at the VLIN5 pin may be as high as 6.5V in shutdown mode (SD
≤ 0.6V).
Note 9: When SS1, SS2 pins are charged above this voltage and either of the output voltage at VOUT1 or VOUT2 is still below the regulation limit, the under voltage
protection feature is initialized.
Note 10: Above this voltage, the under voltage protection is enabled.
Note 11: For each device, there is a 10% (typical) gap of the measured output voltage between the PGOOD signal transitions from high to low and the under voltage
protection is activated. The under voltage protection will not be activated while the PGOOD signal is in the logic HIGH state.
Note 12: During normal shutdown or UVP, LDRV1or LDRV2 pin goes high when VO1, VO2 detects an output voltage below this level.
LM2645
www.national.com
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