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| 型号： | LM9617CCEA-2 |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQCC48 |
| 封装： | LCC-48 |
| 文件页数： | 16/40页 |
| 文件大小： | 408K |
| 代理商： | LM9617CCEA-2 |
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Functional Description (continued)
14.6
Synchronisation Signals in Slave Mode
The sensor’s digital video port’s synchronisation signals can be
programmed to operate in slave mode. In slave mode the inte-
grated timing and control block will only start frame and row pro-
cessing upon the receipt of triggers from an external source.
Only two synchronization signals are used in slave mode as fol-
lows:
hsync
is the row trigger input signal.
vsync
is the frame trigger input signal.
Figure 46 shows the LM9617’s digital video port in slave mode
connected to a digital video processor master DVP.
Figure 46. LM9617 in slave mode
14.7
Row Trigger Input Pin (hsync)
The row trigger input pin, hsync, is used to trigger the process-
ing of a given row. It must be activated for at least two “mclk”
cycle. The first pixel data will appear at d[11:0] “Xmclk“periods
after the assertion of the row trigger, were Xmclk is given by:
Where:
DW
StAd
is the value of the display window column start
address.
The polarity of the active level of the row trigger is programma-
ble. By default it is active high.
14.8
Frame Trigger Input Pin (vsync)
The frame trigger input pin, vsync, is used to reset the row
address counter and prepare the array for row processing. It
must be activated for at least one “mclk” cycle and no more than
96 mclk cycles after the activation of hsync as illustrated in Fig-
ure 48.
The polarity of the active level of the row trigger is programma-
ble. By default it is active high.
RowTrig
FrameTrig
MasterClock
din[11:0]
d[11:0]
hsync
vsync
pclk
mclk
DVP
LM9617
Xmclk = 124 + DWStAd
Figure 47. hsync slave mode timing diagram for centred display window of 642 pixels
Figure 48. vsync slave mode timing diagram for scan window of 504 rows.
779
778
777
776
0
1
3
2
134
135
136
137
779
778
777
0
1
776
775
774
...
hsync
pixel 11
pixel 12
pixel 652
d[11:0]
mclk
count
642 valid pixels
780 clock cycles per line
779
778
777
776
0
1
3
2
779
778
777
0
1
776
775
774
...
hsync
mclk
mclk
count
780 clock cycles per line
internal row
counter
line502
line 502
No more than
96 clock cycles
vsync
...
779
778
777
0
1
776
775
774
line503
line 0
L
M
9
6
1
7
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