参数资料
型号: LM9617CCEA-2
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, CQCC48
封装: LCC-48
文件页数: 5/40页
文件大小: 408K
代理商: LM9617CCEA-2
Confidential
13
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Functional Description (continued)
5.0
SNAPSHOT MODE
The LM9617 is capable of capturing a single frame of an image
under hardware or software control, with or without the aid of an
external
shutter.
Two
registers,
SNAPSHOTMODE0
&
SNAPSHOTMODE1, are provided to program, monitor and con-
trol all snapshot sequences.
5.1
Software Controlled Snapshots
The snapshot mode events can be software controlled by writing
to and reading from the snapshot mode registers over the I
2C
compatible interface.
5.2
Hardware Controlled Snapshots
Two dedicated pins are provided on the LM9617, snapshot &
extsync, allowing the snapshot mode events to be controlled by
hardware. The snapshot pin must be enabled by writing to the
SnapEnable bit of the MCFG0 register.
5.3
Auto Snapshot Mode
In auto snapshot mode (see figure 20), upon the receipt of a
snapshot or FTriggerNow trigger signal, the integrated timing and
control circuit will set the FTriggerEN bit and generate an inter-
nal TRIGGER signal (see figure 19), thus resetting the array one
row at a time. At end of the reset cycle the timing and control cir-
cuit will signal the shutter to open via extsync pin or FtSync bit.
At the end of the programmed integration time the shutter will be
signalled to close, and the pixel read-out will commence as
shown in figure 18a. At the end of the read-out sequence the
FTriggerEN will be automatically reset and the sensor will return
to video capture mode as shown in figure 20.
If an external shutter is not available then at least two frames
need to be taken so that the pixels can be integrated over one
frame as shown in Figure 18b.
To use auto snapshot mode the
SsEngage bit of the
SNAPSHOTMODE1 register must be set to zero.
Note 1:
This wave form shows the snapshot pin programmed to the default pulse mode.
Note 2:
The irq pulse is taken low when the snapshot trigger interrupt flag (SsTrigFlag) in the snapshot mode1 (SNAPMODE1) register is read.
Note 3:
The irq pulse is taken low when the snapshot trigger interrupt flag (SsRdFlag) in the snapshot mode1 (SNAPMODE1 ) register is read.
Figure 18. Snapshot Mode
Start Snapshot Sequence
Start of Array Reset Frames
Open Shutter
Close shutter & start read-out
Read-out complete
FTriggerEn
snapshot or FTriggerNow
extsync or FtSync
FtBusy
Array reset,
irq
programmable 1 to 4 frames
Capture
Data
read-out
image
note1
note2
note 3
Start Snapshot sequence
Start of Array Reset Frames
Integration Start
Start Read-out
Read-out Complete
FTriggerEn
snapshot or FTriggerNow
extsync or FtSync
FtBusy
Bold external pins
italic register bits
Array reset,
irq
programmable 1 to 4 frames
Capture
Data
read-out
image
note 1
note 2
note 3
a) With External Shutter
b) Without External Shutter
L
M
9
6
1
7
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