Supply/Grounding, Layout and
Thermal Recommendations
Power Planes
Power for the LM98640QML should be provided through a
broad plane which is located on one layer adjacent to the
ground plane(s). Placing the power and ground planes on
adjacent layers will provide low impedance decoupling of the
AFE supplies, especially at higher frequencies. The output of
a linear regulator should feed into the power plane through a
low impedance multi-via connection. The power plane should
be split into individual power peninsulas near the AFE. Each
peninsula should feed a particular power bus on the AFE, with
decoupling for that power bus connecting the peninsula to the
ground plane near each power/ground pin pair. Using this
technique can be difficult on many printed circuit CAD tools.
To work around this, zero ohm resistors can be used to con-
nect the power source net to the individual nets for the differ-
ent AFE power buses. As a final step, the zero ohm resistors
can be removed and the plane and peninsulas can be con-
nected manually after all other error checking is completed.
Bypass Capacitors
The general recommendation is to have one 100nF capacitor
for each power/ground pin pair. The capacitors should be
surface mount multi-layer ceramic chip capacitors.
Ground Plane
Grounding should be done using continuous full ground
planes to minimize the impedance for all ground return paths,
and provide the shortest possible image/return path for all
signal traces.
Thermal Management
The exposed pad on bottom of the package is attached to the
back of the die to act as a heat sink. Connecting this pad to
the PCB ground planes with a low thermal resistance path is
the best way to remove heat from the AFE. This pad should
also be connected to the ground planes through low
impedance path for electrical purposes.
Radiation Environments
Careful consideration should be given to environmental con-
ditions when using a product in a radiation environment.
Total Ionizing Dose
Testing and qualification of this product is done on a wafer
level according to MIL-STD-883, Test Method 1019. Wafer
level TID data is available with lot shipments.
Single Event Latch-Up and Functional Interrupt
One time single event latch-up (SEL) and single event func-
tional interrupt (SEFI) testing was preformed according to
EIA/JEDEC Standard, EIA/JEDEC57. SEL testing was con-
ducted with the junction temperature at 125°C. The linear
energy transfer threshold (LETth) shown in the Key Specifi-
cations table on the front page is the maximum LET tested. A
test report is available upon request.
Single Event Effects
A report on single event upset (SEU) is available upon re-
quest.
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LM98640QML