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参数资料
| 型号： | LMX2312USLDX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | XO, clock |
| 英文描述： | PLLatinum⑩ Ultra Low Power Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, QCC20 |
| 封装： | THIN, CSP-20 |
| 文件页数： | 28/29页 |
| 文件大小： | 662K |
| 代理商： | LMX2312USLDX |
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3.0 Programming Description
(Continued)
3.3.3 B_CNTR[12:0]
The NB_CNTR control word is used to program the B counter. The B counter is a 13-bit binary counter used in the programmable
feedback divider. The B counter can be programmed to values ranging from 3 to 8,191. See Section 1.4 for details on how the
value of the B counter should be selected.
B COUNTER
N[19:7]
Divider Value
3
4
8,191
NOTE:
B counter divide ratio must be
≥
3.
B_CNTR[12:0]
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
1
0
1
1
1
1
3.3.4 A_CNTR[4:0]
The NA_CNTR control word is used to program theAcounter. TheAcounter is a 5-bit swallow counter used in the programmable
feedback divider. The A counter can be programmed to values ranging from 0 to 31. See Section 1.4 for details on how the value
of the A counter should be selected.
A Counter
N[6:2]
Divide
Ratio
0
1
31
A_CNTR[4:0]
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
NOTES:
A counter divide ratio must be
≤
P and A counter divide ratio must be
≤
B counter divide ratio.
3.4 T REGISTER
The T register contains the TO_CNTR control word and FoLD2 control bit. The detailed descriptions and programming
information for each control word is discussed in the following sections.
Register
Most Significant Bit
20
19
SHIFT REGISTER BIT LOCATION
14
13
12
Least Significant Bit
4
3
2
21
18
17
16
15
11
10
9
8
7
6
5
1
Address
Field
1
0
Data Field
T
0
0
0
0
0
0
0
FoLD2
TO_CNTR[11:0]
0
3.4.1 FoLD2
See Section 3.2.5 for FoLD Output Truth Table details.
FoLD Output (P/O Output Truth Table)
T[14]
3.4.2 TO_CNTR[11:0]
When the Fastlock Timeout counter (TO_CNTR) is loaded with 0, Fastlock is off, the FL pin will be in TRI-STATE mode, and the
charge pump current will be the value specified by the Charge Pump Magnitude bit, R[18]. When the Timeout counter is loaded
with 1, the FL pin is 0 (pulled low) and the charge pump current will be at the 4X state. When the Timeout counter is loaded with
2, the FL pin will again be set to 0 (pulled low), but the charge pump current will be controlled by R[18]. When the Timeout counter
is loaded with 3, the FL pin is 1 (pulled high) with the charge pump current will be controlled by R[18]. When loaded with 4 through
4095, Fastlock is active and will time-out after the specified number of phase detector events.
Timeout Counter Table
T[13:2]
Count
FL Pin Forced TRI-STATE
FL Pin Forced Low
FL Pin Forced Low
FL Pin Forced High
Min Count (4)
Max Count (4095)
TO_CNTR[11:0]
0
0
0
0
0
0
0
0
0
0
1
1
Notes
C
P
current controlled by R[18]
C
P
= 4 mA (manual Fastlock mode)
C
P
current controlled by R[18]
C
P
current controlled by R[18]
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
C
P
Current set to 4 mA, switches to 1 mA
when count reaches 0
L
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