参数资料
型号: LMX2312USLDX
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: XO, clock
英文描述: PLLatinum⑩ Ultra Low Power Frequency Synthesizer for RF Personal Communications
中文描述: PLL FREQUENCY SYNTHESIZER, 1200 MHz, QCC20
封装: THIN, CSP-20
文件页数: 4/29页
文件大小: 662K
代理商: LMX2312USLDX
Pin Descriptions
(Continued)
Pin Number
11
12
Pin Name
NC
Data
I/O
— No Connect.
I
High impedance CMOS Data input. Serial
Data is entered MSB first. The last two
bits are the address for the target
registers. The Data is internally referenced
to V
μC
.
Description
I/O Circuit Configuration
13
LE
I
High impedance CMOS LE input. When
Latch Enable goes HIGH, data stored in
the 22-bit shift register is loaded into one
the 3 control registers, based on the
address field. The Latch Enable is
internally referenced to V
μC
.
14
15
GND
CE
— Digital ground.
I
High impedance CMOS Chip Enable
input. Provides logical power-down control
of the device. Pull-up to V
μC
if unused.
The Chip Enable is internally referenced
to V
μC
.
16
V
μC
— Power supply for MICROWIRE
circuitry.
Must be
V
CC
. Typically connected to
same supply level as microprocessor or
baseband controller to enable
programming at low voltages.
— No Connect.
— Power supply voltage input. Input may
range from 2.7V to 5.5V. Bypass
capacitors should be placed as close as
possible to this pin and be connected
directly to the ground plane.
O Fastlock mode output. In Fastlock mode
this pin is at logic low. When not in
Fastlock mode, this pin is in TRI-STATE
mode. This pin can also be forced to
TRI-STATE, forced low or forced high by
the programming of the first two-bits of the
Timeout Counter.
— Power supply for charge pump. Must be
V
CC
.
17
18
NC
V
CC
19
FL
20
V
P
L
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