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参数资料
| 型号： | LMX2353TMX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | XO, clock |
| 英文描述： | PLLatinum⑩ Fractional N Single 2.5 GHz Frequency Synthesizer |
| 中文描述： | PHASE LOCKED LOOP, 2500 MHz, PDSO16 |
| 封装： | PLASTIC, TSSOP-16 |
| 文件页数： | 6/16页 |
| 文件大小： | 210K |
| 代理商： | LMX2353TMX |
1.0 Functional Description
(Continued)
1.10 POWER CONTROL
The PLL is power controlled by the device enable pin (CE) or MICROWIRE power down bit. The enable pin overrides the power
down bit
except for the V2_EN bit.
When CE is high, the power down bit determines the state of power control. Activation of any
PLL power down mode results in the disabling of the N counter and de-biasing of f
input (to a high impedance state). The R
counter functionality also becomes disabled when the power down bit is activated. The reference oscillator block powers down
and the OSCin pin reverts to a high impedance state when CE or power down bit’s are asserted,
unless the V2_EN bit (R[20])
is high
. Power down forces the charge pump and phase comparator logic to a TRI-STATE condition.Apower down counter reset
function resets both N and R counters. Upon powering up the N counter resumes counting in “close” alignment with the R counter
(The maximum error is one prescaler cycle). The MICROWIRE control register remains active and capable of loading and latching
in data during all of the power down modes.
2.0 Programming Description
2.1 MICROWIRE INTERFACE
The LMX2353 register set can be accessed through the MICROWIRE interface. A 24-bit shift register is used as a temporary reg-
ister to indirectly program the on-chip registers. The shift register consists of a 24-bit DATA[21:0] field and a 2-bit ADDRESS[1:0]
field as shown below. The address field is used to decode the internal register address. Data is clocked into the shift register in
the direction from MSB to LSB, when the CLOCK signal goes high. On the rising edge of Latch Enable (LE) signal, data stored
in the shift register is loaded into the addressed latch.
MSB
LSB
DATA[21:0]
ADDRESS[1:0]
23
2
1
0
2.1.1 Registers’ Address Map
When Latch Enable (LE) is transitioned high, data is transferred from the 24-bit shift register into the appropriate latch depending
on the state of the ADDRESS[1:0] bits. A multiplexing circuit decodes these address bits and writes the data field to the corre-
sponding internal register.
ADDRESS[1:0]
FIELD
0
0
1
1
REGISTER
ADDRESSED
F1 Register
F2 Register
R Register
N Register
0
1
0
1
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相关代理商/技术参数 |
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|---|---|
| LMX2353TMX/NOPB | 功能描述:IC FREQ SYNTH 2.5GHZ 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:PLLatinum™ 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| LMX2354 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer |
| LMX2354SLB | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer |
| LMX2354SLBX | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| LMX2354SLBX/NOPB | 功能描述:IC FREQ SYNTH DUAL 24-LAMCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:PLLatinum™ 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
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