参数资料
型号: LP3906SQXVPFP
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 稳压器
英文描述: 2 A DUAL SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, QCC24
封装: 5 X 4 MM, 0.80 MM HEIGHT, LLP-24
文件页数: 7/40页
文件大小: 4197K
代理商: LP3906SQXVPFP
DC/DC Converters
OVERVIEW
The LP3906 supplies the various power needs of the application by means of two Linear Low Drop Regulators LDO1 and LDO2
and two Buck converters SW1 and SW2. The table here under lists the output characteristics of the various regulators.
SUPPLY SPECIFICATION
Supply
Load
Output
V
OUT Range(V)
Resolution (mV)
I
MAX
Maximum Output Current
(mA)
LDO1
analog
1.0 to 3.5
100
300
LDO2
analog
1.0 to 3.5
100
300
SW1
digital
0.8 to 2.0
50
1500
SW2
digital
1.0 to 3.5
100
1500
*For default values of the regulators, please consult Default Voltage Options Table page 3
LINEAR LOW DROP-OUT REGULATORS (LDOS)
LDO1 and LDO2 are identical linear regulators targeting ana-
log loads characterized by low noise requirements. LDO1 and
LDO2 are enabled through the ENLDO pin or through the
corresponding LDO1 or LDO2 control register. The output
voltages of both LDOs are register programmable. The de-
fault output voltages are factory programmed during Final
Test, which can be tailored to the specific needs of the system
designer.
20197822
NO-LOAD STABILITY
The LDOs will remain stable and in regulation with no external
load. This is an important consideration in some circuits, for
example CMOS RAM keep-alive applications.
LDO1 AND LDO2 CONTROL REGISTERS
LDO1 and LDO2 can be configured by means of the LDO1
and LDO2 control registers. The output voltage is pro-
grammable in steps of 100mV from 1.0V to 3.5V by program-
ming bits D4-0 in the LDO Control registers. Both LDO1 and
LDO2 are enabled by applying a logic 1 to the ENLDO1 and
ENLDO2 pin. Enable/disable control is also provided through
enable bit of the LDO1 and LDO2 control registers. The value
of the enable LDO bit in the register is logic 1 by default. The
output voltage can be altered while the LDO is enabled.
15
www.national.com
LP3906
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