参数资料
型号: LP3907SQ-JIXI
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 稳压器
英文描述: 1.5 A DUAL SWITCHING CONTROLLER, 2100 kHz SWITCHING FREQ-MAX, QCC24
封装: 4 X 4 MM, 0.8 MM HEIGHT, LLP-24
文件页数: 21/44页
文件大小: 3058K
代理商: LP3907SQ-JIXI
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledged related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9th clock pulse, signifying acknowledgement.
A receiver which has been addressed must generate an ac-
knowledgement (“ACK”) after each byte has been received.
After the START condition, the I2C master sends a chip ad-
dress. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). Please note that ac-
cording to industry I2C standards for 7-bit addresses, the MSB
of an 8-bit address is removed, and communication actually
starts with the 7th most significant bit. For the eighth bit (LSB),
a “0” indicates a WRITE and a “1” indicates a READ. The
second byte selects the register to which the data will be writ-
ten. The third byte contains data to write to the selected
register.
The LP3907 has factory-programmed I2C addresses. The
LLP chip has a chip address of 60'h, while the micro SMD chip
has a chip address of 61'h.
30017818
I2C Chip Address (see note above)
30017819
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = LP3907 LLP chip address: 0x60; micro SMD chip address: 0x61
I2C Write Cycle
When a READ function is to be accomplished, a WRITE func-
tion must precede the READ function, as shown in the Read
Cycle waveform.
30017824
I2C Read Cycle
www.national.com
28
LP3907
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