参数资料
型号: LP3907SQ-JIXI
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 稳压器
英文描述: 1.5 A DUAL SWITCHING CONTROLLER, 2100 kHz SWITCHING FREQ-MAX, QCC24
封装: 4 X 4 MM, 0.8 MM HEIGHT, LLP-24
文件页数: 33/44页
文件大小: 3058K
代理商: LP3907SQ-JIXI
Capacitor
Min Value
Unit
Description
Recommended Type
C
LDO1
0.47
F
LDO1 output capacitor
Ceramic, 6.3V, X5R
C
LDO2
0.47
F
LDO2 output capacitor
Ceramic, 6.3V, X5R
C
SW1
10.0
F
SW1 output capacitor
Ceramic, 6.3V, X5R
C
SW2
10.0
F
SW2 output capacitor
Ceramic, 6.3V, X5R
I2C Pullup Resistor
Both SDA and SCL terminals need to have pullup resistors
connected to VINLDO12 or to the power supply of the I2C
master. The values of the pull-up resistors (typ.
1.8k) are
determined by the capacitance of the bus. Too large of a re-
sistor combined with a given bus capacitance will result in a
rise time that would violate the max. rise time specification. A
too small resistor will result in a contention with the pull-down
transistor on either slave(s) or master.
Operation without I2C Interface
Operation of the LP3907 without the I2C interface is possible
if the system can operate with default values for the LDO and
Buck regulators. (Read below: Factory programmable op-
tions). The I2C-less system must rely on the correct default
output values of the LDO and Buck converters.
Factory Programmable Options
The following options are EPROM programmed during final
test of the LP3907. The system designer that needs specific
options is advised to contact the local National Semiconduc-
tor sales office.
Factory programmable
options
Current value
Enable delay for power on
code 010 (see Control 1
register section)
SW1 ramp speed
8 mV/s
SW2 ramp speed
8 mV/s
The I2C Chip ID address is offered as a metal mask option.
The current address for the LLP chip equals 0x60, while the
address for the micro SMD chip is 0x61.
HIGH V
IN HIGH-LOAD OPERATION
Additional information is provided when the IC is operated at
extremes of V
IN and regulator loads. These are described in
terms of the Junction temperature and, Buck output ripple
management.
JUNCTION TEMPERATURE
The maximum junction temperature T
J-MAX-OP of 125C of the
IC package.
The following equations demonstrate junction temperature
determination, ambient temperature T
A-MAX and Total chip
power must be controlled to keep T
J below this maximum:
TJ-MAX-OP
= T
A-MAX + (θJA) [ °C/ Watt] * (PD-MAX) [Watts]
Total IC power dissipation P
D-MAX is the sum of the individual
power dissipation of the four regulators plus a minor amount
for chip overhead. Chip overhead is Bias, TSD & LDO analog.
PD-MAX
= P
LDO1 + PLD02 + PBUCK1 + PBUCK2 + (0.0001A * VIN)
[Watts].
Power dissipation of LDO1
P
LDO1 = (VINLDO1- VOUTLDO1) * IoutLDO1 [V*A]
Power dissipation of LDO2
P
LDO2 = (VINLDO2 - VoutLDO2) * IoutLDO2 [V*A]
Power dissipation of Buck1
P
Buck1 = PIN – POUT =
Vout
Buck1* IoutBuck1 * (1 -η
1) / η1 [V*A]
η1 = efficiency of buck 1
Power dissipation of Buck2
P
Buck2 = PIN – POUT =
Vout
Buck2 * IoutBuck2 * (1 - η
2) / η2 [V*A]
η2 = efficiency of Buck2
Where
η is the efficiency for the specific condition taken from
efficiency graphs.
39
www.national.com
LP3907
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