LP62S16128CU-70LLI PDF资料下载(1/14 页)128K X 16 BIT LOW VOLTAGE CMOS SRAM

您好，
买卖IC网欢迎您。
请登录
免费注册

您现在的位置：买卖IC网 > PDF目录299411 > LP62S16128CU-70LLI (AMIC Technology Corporation) 128K X 16 BIT LOW VOLTAGE CMOS SRAM PDF资料下载

参数资料

型号：	LP62S16128CU-70LLI
厂商：	AMIC Technology Corporation
元件分类：	SRAM
英文描述：	128K X 16 BIT LOW VOLTAGE CMOS SRAM
中文描述：	128K的× 16位低电压CMOS的SRAM
文件页数：	1/14页
文件大小：	160K
代理商：	LP62S16128CU-70LLI

当前第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页

LP62S16128B-I Series

128K X 16 BIT LOW VOLTAGE CMOS SRAM

(August, 2001, Version 1.0)

AMIC Technology, Inc.

Features

n Operating voltage: 2.7V to 3.6V

n Access times: 55/70 ns (max.)

n Current:

Very low power version: Operating: 55ns 40mA (max.)

70ns 35mA (max.)

Standby:

A (max.)

n Full static operation, no clock or refreshing required

n All inputs and outputs are directly TTL-compatible

n Common I/O using three-state output

n Data retention voltage: 2V (min.)

n Available in 44-pin TSOP and 48-ball CSP (6 x 8 mm)

packages

General Description

The LP62S16128B-I is a low operating current 2,097,152-

bit static random access memory organized as 131,072

words by 16 bits and operates on low power voltage from

2.7V to 3.6V. It is built using AMIC's high performance

CMOS process.

Inputs and three-state outputs are TTL compatible and

allow for direct interfacing with common system bus

structures.

The chip enable input is provided for POWER-DOWN,

device enable. Two byte enable inputs and an output

enable input are included for easy interfacing.

Data retention is guaranteed at a power supply voltage

as low as 2V.

Pin Configurations

n TSOP

n CSP (Chip Size Package)

48-pin Top View

I/O9

I/O10

GND

VCC

I/O15

I/O16

A12

A10

A11

A13

A14

A15

I/O8

I/O7

I/O3

I/O1

GND

VCC

I/O14

I/O13

I/O12

I/O11

A16

I/O2

I/O4

I/O5

I/O6