参数资料
型号: LPC11U12FBD48/201,
厂商: NXP Semiconductors
文件页数: 29/72页
文件大小: 0K
描述: IC MCU 32BIT 16K 48LQFP
产品培训模块: Code Density for LPC11xx
标准包装: 250
系列: LPC11Uxx
核心处理器: ARM? Cortex?-M0
芯体尺寸: 32-位
速度: 50MHz
连通性: I²C,Microwire,智能卡,SPI,SSP,UART/USART,USB
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 40
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
RAM 容量: 6K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-LQFP
包装: 托盘
其它名称: 568-8582
LPC11U1X
All information provided in this document is subject to legal disclaimers.
NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.2 — 11 March 2014
35 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
[1]
The ADC is monotonic, there are no missing codes.
[2]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 7.
[3]
The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 7.
[4]
The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 7.
[5]
The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 7.
[6]
The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 7.
[7]
Tamb = 25 C; maximum sampling frequency fs = 400kSamples/s and analog input capacitance Cia = 1 pF.
[8]
Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs Cia).
Table 7.
ADC static characteristics
Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIA
analog input voltage
0
-
VDD
V
Cia
analog input capacitance
-
1
pF
ED
differential linearity error
1LSB
EL(adj)
integral non-linearity
1.5
LSB
EO
offset error
3.5
LSB
EG
gain error
[5] --0.6
%
ET
absolute error
4LSB
Rvsi
voltage source interface
resistance
--40
k
Ri
input resistance
[7][8] --2.5
M
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