参数资料
型号: LPC11U12FBD48/201,
厂商: NXP Semiconductors
文件页数: 43/72页
文件大小: 0K
描述: IC MCU 32BIT 16K 48LQFP
产品培训模块: Code Density for LPC11xx
标准包装: 250
系列: LPC11Uxx
核心处理器: ARM? Cortex?-M0
芯体尺寸: 32-位
速度: 50MHz
连通性: I²C,Microwire,智能卡,SPI,SSP,UART/USART,USB
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 40
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
RAM 容量: 6K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-LQFP
包装: 托盘
其它名称: 568-8582
LPC11U1X
All information provided in this document is subject to legal disclaimers.
NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.2 — 11 March 2014
48 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
[8]
The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or
tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[9]
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
Fig 22. I2C-bus pins clock timing
002aaf425
tf
70 %
30 %
SDA
tf
70 %
30 %
S
70 %
30 %
70 %
30 %
tHD;DAT
SCL
1 / fSCL
70 %
30 %
70 %
30 %
tVD;DAT
tHIGH
tLOW
tSU;DAT
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