参数资料
型号: LPC11U13FBD48/201,
厂商: NXP Semiconductors
文件页数: 18/72页
文件大小: 0K
描述: IC MCU 32BIT 24K 48LQFP
产品培训模块: Code Density for LPC11xx
标准包装: 250
系列: LPC11Uxx
核心处理器: ARM? Cortex?-M0
芯体尺寸: 32-位
速度: 50MHz
连通性: I²C,Microwire,智能卡,SPI,SSP,UART/USART,USB
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 40
程序存储器容量: 24KB(24K x 8)
程序存储器类型: 闪存
RAM 容量: 6K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-LQFP
包装: 托盘
其它名称: 568-8563
LPC11U1X
All information provided in this document is subject to legal disclaimers.
NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.2 — 11 March 2014
25 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
7.16.1.2
System oscillator
The system oscillator can be used as the clock source for the CPU, with or without using
the PLL. On the LPC11U1x, the system oscillator must be used to provide the clock
source to USB.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
7.16.1.3
Watchdog oscillator
The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and
temperature is
40 % (see also Table 13).
7.16.2 System PLL and USB PLL
The LPC11U1x contain a system PLL and a dedicated PLL for generating the 48 MHz
USB clock. The system and USB PLLs are identical.
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The output
divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output
frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.
The PLL settling time is 100
s.
7.16.3 Clock output
The LPC11U1x features a clock output function that routes the IRC oscillator, the system
oscillator, the watchdog oscillator, or the main clock to an output pin.
7.16.4 Wake-up process
The LPC11U1x begin operation at power-up and when awakened from Deep power-down
mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation
to resume quickly. If the main oscillator or the PLL is needed by the application, software
will need to enable these features and wait for them to stabilize before they are used as a
clock source.
7.16.5 Power control
The LPC11U1x support a variety of power control features. There are four special modes
of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode. The CPU clock rate may also be controlled as needed by
changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider
value. This allows a trade-off of power versus processing speed based on application
requirements. In addition, a register is provided for shutting down the clocks to individual
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