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参数资料
| 型号： | LPC2106FHN48,551 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 11/41页 |
| 文件大小： | 0K |
| 描述： | IC ARM7 MCU FLASH 128K 48-HVQFN |
| 标准包装： | 260 |
| 系列： | LPC2100 |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 60MHz |
| 连通性： | I²C，Microwire，SPI，SSI，SSP，UART/USART |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 32 |
| 程序存储器容量： | 128KB（128K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 64K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.65 V ~ 3.6 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 包装： | 管件 |
| 配用： | 622-1019-ND - BOARD FOR LPC2106 48-LQFP 622-1008-ND - BOARD FOR LPC9103 10-HVSON 568-1756-ND - BOARD EVAL FOR LPC210X ARM MCU |
| 其它名称： | 568-1324 935274661551 LPC2106FHN48-S |
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LPC2104_2105_2106_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 20 June 2008
19 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.14.1 Features
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
Up to four (Timer 1) and three (Timer 0) 32-bit capture channels, that can take a
snapshot of the timer value when an input signal transitions. A capture event may also
optionally generate an interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four (Timer 1) and three (Timer 0) external outputs corresponding to match
registers, with the following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
6.14.2 Features available in LPC2104/2105/2106/01 only
The LPC2104/2105/2106/01 can count external events on one of the capture inputs if the
external pulse lasts at least one half of the period of the PCLK. In this conguration,
unused capture lines can be selected as regular timer capture inputs or used as external
interrupts.
Timer can count cycles of either the peripheral clock (PCLK) or an externally supplied
clock.
When counting cycles of an externally supplied clock, only one of the timer’s capture
inputs can be selected as the timer’s clock. The rate of such a clock is limited to
PCLK
4. Duration of HIGH/LOW levels on the selected CAP input cannot be shorter
than 1
(2PCLK).
6.15 Watchdog timer
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the Watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the Watchdog within a predetermined
amount of time.
6.15.1 Features
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
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相关代理商/技术参数 |
参数描述 |
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| LPC2109 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Single-chip 16/32-bit microcontrollers; 64/128/256 kB ISP/IAP flash with 10-bit ADC and CAN |
| LPC2109_11 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Single-chip 16/32-bit microcontrollers; 64/128/256 kB ISP/IAP flash with 10-bit ADC and CAN |
| LPC2109FBD01 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Single-chip 16/32-bit microcontrollers; 64/128/256 kB ISP/IAP flash with 10-bit ADC and CAN |
| LPC2109FBD64 | 制造商:NXP Semiconductors 功能描述:MCU 32BIT ARM7 64K FLASH LQFP64 制造商:NXP Semiconductors 功能描述:MCU 32BIT ARM7 64K FLASH, LQFP64 |
| LPC2109FBD64/00 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Single-chip 16/32-bit microcontrollers; 64/128/256 kB ISP/IAP flash with 10-bit ADC and CAN |
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