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参数资料
| 型号： | LSM2-T/6-W3NG-C |
| 元件分类： | 电源模块 |
| 英文描述： | 1-OUTPUT 19.8 W DC-DC REG PWR SUPPLY MODULE |
| 封装： | ROHS COMPLIANT |
| 文件页数： | 6/17页 |
| 文件大小： | 1394K |
| 代理商： | LSM2-T/6-W3NG-C |
LSM2 Series
Single Output, Non-isolated, Selectable-Output POL DC/DC Converters
MDC_LSM2_A01 Page 4 of 7
P O W E R E L E C T R O N I C S D I V I S I O N
D C / D C C O N V E R T E R S
www.cd4power.com
Figure 14. Wiring for Simultaneous Phasing
Figure 15. Self-Ramping Power Up
Figure 16. Proportional Phasing
Figure 17. Sequence/Track Simplified Equivalent Schematic
Figure 4 shows a basic Master (POL A) and Slave (POL B) connected so the
POL B ramps up identically to POL A as shown in timing diagram, Figure 0.
RC network R and C charge up at a rate set by the R-C time constant,
giving a roughly linear ramp. As POL A reaches 3.3VOUT (the setpoint of POL
B), POL B will stop rising. POL A then continues rising until it reaches 5V. R
should be significantly smaller than the internal bias current resistor from the
Sequence pin. Start with a 20k
W value. We assume that the critical phase is
only on power up therefore there is no provision for ramped power down.
Figure 5 shows a single POL and the same RC network. However, we have
added a FET at Q as an up/down control. When VIN power is applied to the
POL, Q is biased on, shorting out the Sequence pin. When Q’s gate is biased
off, R charges C and the POL’s output ramps up at the R-C slew rate.
Note: Q’s gate would typically be controlled from some external digital logic.
Guidelines for Sequence/Track Applications
[] Leave the converter’s On/Off Enable control (if installed) in the On setting.
Normally, you should just leave the On/Off pin open.
[2] Allow the converter to stabilize (typically less than 20 mS after +VIN
power on) before raising the Sequence input. Also, if you wish to have a
ramped power down, leave +VIN powered all during the down ramp. Do
not simply shut off power.
[3] If you do not use the Sequence/Track pin, leave it open or tied to +VIN.
[4] Observe the Output slew rate relative to the Sequence input. A rough
guide is 2 Volts per millisecond maximum slew rate. If you exceed this
slew rate on the Sequence pin, the converter will simply ramp up at
it’s maximum output slew rate (and will not necessarily track the faster
Sequence input). The reason to carefully consider the slew rate limitation
is in case you want two different POL’s to precisely track each other.
If you wish to have a ramped power down (rather than a step down), add a
small resistor in series with Q’s drain.
Figure 6 shows both a RC ramp on Master POL A and a proportional tracking
divider (R2 and R3) on POL B. We have also added an optional very small
noise filter cap at C2. Figure 6’s circuit corresponds roughly to Figure ’s
timing for power up.
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