参数资料
型号: LT1016IS8#PBF
厂商: Linear Technology
文件页数: 4/20页
文件大小: 0K
描述: IC COMPARATOR 10NS HI-SPD 8-SOIC
标准包装: 100
系列: UltraFast™
类型: 带锁销
元件数: 1
输出类型: CMOS,补充型,TTL
电压 - 输入偏移(最小值): 3mV @ ±5V
电流 - 输入偏压(最小值): 10µA @ ±5V
电流 - 输出(标准): 20mA
电流 - 静态(最大值): 35mA
CMRR, PSRR(标准): 96dB CMRR,75dB PSRR
传输延迟(最大): 14ns
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
安装类型: 表面贴装
包装: 管件
LT1016
12
1016fc
applicaTions inForMaTion
Another output-caused fault is shown in Figure 13. The
output transitions are initially correct but end in a ringing
condition. The key to the solution here is the ringing. What
is happening is caused by an output lead that is too long.
The output lead looks like an unterminated transmission
line at high frequencies and reflections occur. This ac-
counts for the abrupt reversal of direction on the leading
edge and the ringing. If the comparator is driving TTL this
may be acceptable, but other loads may not tolerate it. In
this instance, the direction reversal on the leading edge
might cause trouble in a fast TTL load. Keep output lead
lengths short. If they get much longer than a few inches,
terminate with a resistor (typically 250 to 400).
200ns-0.01% Sample-and-Hold Circuit
Figure 14’s circuit uses the LT1016’s high speed to
improve upon a standard circuit function. The 200ns
acquisition time is well beyond monolithic sample-and-
hold capabilities. Other specifications exceed the best
commercial unit’s performance. This circuit also gets
around many of the problems associated with standard
sample-and-holdapproaches,includingFETswitcherrors
and amplifier settling time. To achieve this, the LT1016’s
high speed is used in a circuit which completely abandons
traditional sample-and-hold methods.
Important specifications for this circuit include:
Acquisition Time
<200ns
Common Mode Input Range
±3V
Droop
1V/s
Hold Step
2mV
Hold Settling Time
15ns
Feedthrough Rejection
>>100dB
When the sample-and-hold line goes low, a linear ramp
starts just below the input level and ramps upward. When
therampvoltagereachestheinputvoltage,A1shutsoffthe
ramp, latches itself off and sends out a signal indicating
sampling is complete.
Figure 14. 200ns Sample-and-Hold
Figure 13. Lengthy, Unterminated Output Lines
Ring from Reflections
1V/DIV
50ns/DIV
1016 F13
+
1k
DELAY
COMP
1N4148
8pF
100
390
470
100
300
Q1
2N5160
Q3
2N2369
Q6
2N2222
Q2
2N2907A
5.1k
1.5k
0.1F
1000pF
(POLYSTYRENE)
390
1k
SN7402
NOW
A1
LT1016
SAMPLE-HOLD
COMMAND (TTL)
OUTPUT
–5V
5V
–15V
INPUT
3V
220
1.5k
Q5
2N2222
LT1009
2.5V
820
1016 F14
Q7
2N5486
LATCH
Q4
2N2907A
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