参数资料
型号: LT1185CT#PBF
厂商: Linear Technology
文件页数: 9/16页
文件大小: 0K
描述: IC REG LDO NEG ADJ 3A TO220
产品培训模块: More Information on LDOs
标准包装: 50
稳压器拓扑结构: 负,可调式
输出电压: -2.5 V ~ -25 V
输入电压: -4.2 V ~ -35 V
电压 - 压降(标准): 0.67V @ 3A
稳压器数量: 1
电流 - 输出: 3A
电流 - 限制(最小): 可调式
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: TO-220-5 成形引线
供应商设备封装: TO-220-5
包装: 管件
产品目录页面: 1326 (CN2011-ZH PDF)
LT1185
APPLICATIO S I FOR ATIO
for remote sense applications, they may need to be con-
sidered. Ground lead resistance of 0.4 ? would cause an
output voltage error of up to (3A/40)(0.4 ? ) = 30mV, or
0.6% at V OUT = 5V. Note that if the sense leads are
connected as shown in Figure 2, with r a ≈ 0 ? , this error is
a fixed number of millivolts, and does not increase as a
function of DC output voltage.
Shutdown Techniques
The LT1185 can be shut down by open-circuiting the REF
pin. The current flowing into this pin must be less than
0.4 μ A to guarantee shutdown. Figure 3 details several
ways to create the “open” condition, with various logic
levels. For variations on these schemes, simply remember
that the voltage on the REF pin is 2.4V negative with
respect to the ground pin.
Output Overshoot
Very high input voltage slew rate during start-up may
cause the LT1185 output to overshoot. Up to 20% over-
shoot could occur with input voltage ramp-up rate exceed-
ing 1V/ μ s. This condition cannot occur with normal 50Hz
5V Logic, Positive Regulated Output
to 400Hz rectified AC inputs because parasitic resistance
and inductance will limit rate of rise even if the power
switch is closed at the peak of the AC line voltage. This
assumes that the switch is in the AC portion of the circuit.
If instead, a switch is placed directly in the regulator input
so that a large filter capacitor is precharged, fast input slew
rates will occur on switch closure. The output of the
regulator will slew at a rate set by current limit and output
capacitor size; dVdt = I LIM /C OUT . With I LIM = 3.6A and C OUT
= 2.2 μ F, the output will slew at 1.6V/ μ s and overshoot can
occur. This overshoot can be reduced to a few hundred
millivolts or less by increasing the output capacitor to
10 μ F and/or reducing current limit so that output slew rate
is held below 0.5V/ μ s.
A second possibility for creating output overshoot is
recovery from an output short. Again, the output slews at
a rate set by current limit and output capacitance. To avoid
overshoot, the ratio I LIM /C OUT should be less than
0.5 × 10 6 . Remember that load capacitance can be added
to C OUT for this calculation. Many loads will have multiple
supply bypass capacitors that total more than C OUT .
5V Logic, Negative Regulated Output
+
R LIM ?
4k
R1
+ V OUT
5V
*
5V
“HI” = OUTPUT “OFF”
V IN
REF
LT1185
GND
FB
R2
+
R5
300k
Q1
2N3906
3 EA 1N4148
Q1
2N3906
V OUT
R4
33k
R LIM
V IN
REF
GND
FB
LT1185 ? F3a
FOR HIGHER VALUES OF R LIM , MAKE R7 = (R LIM )(0.6)
R7
2.4k ?
R6
30k
*CMOS LOGIC
?
V IN
V IN
LT1185
V OUT
LT1185 ? F03b
Figure 3. Shutdown Techniques
1185ff
9
相关PDF资料
PDF描述
LT1085CT-3.3#PBF IC REG LDO 3.3V 3A TO-220-3
ADP1711AUJZ-0.9-R7 IC REG LDO 0.9V .15A TSOT-23-5
HMC15DREH-S93 CONN EDGECARD 30POS .100 EYELET
GSC17DRTN-S13 CONN EDGECARD 34POS .100 EXTEND
GMC17DRTN-S13 CONN EDGECARD 34POS .100 EXTEND
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