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| 型号： | LT1186FIS#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC SW REG CCFL DAC PROG 16SOIC |
| 标准包装： | 2,500 |
| 系列： | Bits-to-Nits™ |
| 类型： | CCFL 控制器 |
| 频率： | 175 ~ 225 kHz |
| 电流 - 电源： | 6mA |
| 电源电压： | 3 V ~ 6.5 V |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
LT1186F
APPLICATIO N S I N FOR M ATIO N
circuitry provides a ratio of switch current to driver current
of about 50:1.
8-Bit Current Output DAC
The 8-bit current output DAC is guaranteed monotonic and
is digitally adjustable by the 8-bit counter in 256 equal
steps. On power up, the counter resets to 80H and the DAC
assumes its mid-range value. The current output I OUT
POWER ON
V CC
CS ALWAYS HIGH
D IN ALWAYS HIGH
LT1186F ? F01c
Figure 1c. Pulse Mode Setup (Increment Only)
drives the I CCFL pin and sets control current for the lamp
current programming block. The DAC has its own 1.24V
bandgap reference and a voltage to current converter that
is trimmed at wafer sort to provide the precision full-scale
current reference. Over temperature, the current output of
the DAC is 50 μ A ± 6%.
POWER ON
V CC
CS ALWAYS HIGH
UP/DN
Digital Interface
UP/DN EVER GOES LOW
LT1186F ? F01d
On power-up, a logic high at CS configures the DAC into
pulse mode. If CS is ever pulled low, the chip configures
into SPI mode until V CC resets. On power-up in pulse
mode, a logic high at D IN puts the counter into increment-
only mode. If UP/DN (D IN ) is ever pulled low, the counter
configures into increment/decrement mode until V CC re-
sets. These modes are illustrated in Figure 1.
SINGLE DAC
Figure 1d. Pulse Mode Setup (Increment/Decrement)
Standard SPI Mode
Refer to the serial interface operating sequence in Figure
2. A falling edge at CS initiates the data transfer. After the
falling CS is recognized, D OUT comes out of three-state.
The clock (CLK) synchronizes the data transfer. Each input
bit shifts into D IN beginning with the MSB on the rising CLK
CS EVER
GOES LOW
CS STAYS
HIGH
edge and each previous data bit shifts out of D OUT begin-
ning with the MSB on the falling CLK edge. After the 8-bit
serial input data is shifted in, a rising edge at CS transfers
SPI MODE
D IN (UP/DN)
EVER GOES
LOW
INCREMENT/
DECREMENT
PULSE MODE
D IN STAYS
HIGH
INCREMENT-
ONLY
the data into the counter, the DAC assumes the new value
I OUT = (8-bit serial input data)(50 μ A)/255 and the D OUT pin
returns to a high impedance state.
1-Wire Interface (Pulse Mode)
LT1186F ? F01a
Figure 1a. Tree Diagram (LT1186F DAC Operating Modes)
In increment-only pulse mode, each rising edge of CLK
increments the upper six bits of the counter by one count.
When incremented beyond 11111100B, the counter rolls
POWER ON
12
CS EVER GOES LOW
Figure 1b. SPI Mode Setup
V CC
CS
LT1186F ? F01b
over and sets the DAC to the minimum value 00000000B.
Therefore, a single pulse applied to CLK increases the
upper 6-bit counter by one-step, and 63 pulse applied to
CLK decreases the counter by one-step. The last two LSBs
are always zero in this mode. I OUT = (B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 )
(50 μ A)/255. The upper 6-bit counter = B 7 B 6 B 5 B 4 B 3 B 2 and
B 1 = B 0 = 0. To configure the LT1186F into increment-only
mode, tie CS and D IN to V CC .
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