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| 型号： | LT1186FIS#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | IC SW REG CCFL DAC PROG 16SOIC |
| 标准包装： | 2,500 |
| 系列： | Bits-to-Nits™ |
| 类型： | CCFL 控制器 |
| 频率： | 175 ~ 225 kHz |
| 电流 - 电源： | 6mA |
| 电源电压： | 3 V ~ 6.5 V |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
LT1186F
APPLICATIO N S I N FOR M ATIO N
CS
t CSLO
t CSHI
CLK
t CKS
t CKHI
t CSH
t CSS
t DS
t DH
t CKLO
t CKH
D IN
D7
D6
D5
D4
D3
D2
D1
D0
t DV
t DO
t DZ
D OUT
Hi-Z
D7 ′
D6 ′
D5 ′
D4 ′
D3 ′
D2 ′
D1 ′
D0 ′
D7
Hi-Z
LT1186F ? F02
Figure 2. SPI Interface Timing Specification
2-Wire Interface (Pulse Mode)
In increment/decrement pulse mode, a logic high at UP/
DN programs the counter into increment mode and each
rising edge of CLK increments the upper six bits of the
counter by one. The counter stops incrementing at
11111100B. A logic low at UP/DN programs the counter
into decrement mode and each rising edge of CLK decre-
ments the upper six bits of the counter by one. The counter
stops decrementing at 00000000B. The last two LSBs are
always zero in this mode. I OUT = (B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 )
(50 μ A)/255. The upper 6-bit counter = B 7 B 6 B 5 B 4 B 3 B 2 and
B 1 = B 0 = 0. To configure the LT1186F into increment/
decrement mode, tie CS to V CC and pulse the UP/DN pin
once on power-up.
Simplified Lamp Current Programming
A programming block in the LT1186F controls lamp
current, permitting either grounded lamp or floating lamp
configurations. Grounded configurations control lamp
current by directly controlling one-half of actual lamp
current and converting it to a feedback signal to close a
control loop. Floating configurations control lamp current
by directly controlling the Royer’s primary-side converter
current and generating a feedback signal to close a control
loop.
Previous backlighting solutions have used a traditional
error amplifier in the control loop to regulate lamp current.
This approach converted an RMS current into a DC voltage
for the input of the error amplifier. This approach used
several time constants in order to provide stable loop
frequency compensation. This compensation scheme
meant that the loop had to be fairly slow and that output
overshoot with start-up or overload conditions had to be
carefully evaluated in terms of transformer stress and
breakdown voltage requirements.
The LT1186F eliminates the error amplifier concept en-
tirely and replaces it with a lamp current programming
block. This block provides an easy-to-use interface to
program lamp current. The programmer circuit also re-
duces the number of time constants in the control loop by
combining the error signal conversion scheme and fre-
quency compensation into a single capacitor. The control
loop thus exhibits the response of a single pole system,
allows for faster loop transient response and virtually
eliminates overshoot under start-up or overload condi-
tions.
Lamp current is programmed at the input of the program-
mer block, the I CCFL pin. This pin is the input of a shunt
regulator and accepts a DC input current signal of 0 μ A to
50 μ A from the DAC. This input signal is converted to a 0 μ A
to 250 μ A source current at the CCFL V C pin. The program-
mer circuit is simply a current-to-current converter with a
gain of five. The typical input current programming range
for 0mA to 6mA lamp current is 0 μ A to 50 μ A.
The I CCFL pin is sensitive to capacitive loading and will
oscillate with capacitance greater than 10pF. For example,
loading the I CCFL pin with a 1 × or 10 × scope probe causes
oscillation and erratic CCFL regulator operation because
of the probe’s respective input capacitance. A current
meter in series with the I CCFL pin will also produce oscil-
13
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