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参数资料
| 型号： | LT1186FIS#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/16页 |
| 文件大小： | 0K |
| 描述： | IC SW REG CCFL DAC PROG 16SOIC |
| 标准包装： | 2,500 |
| 系列： | Bits-to-Nits™ |
| 类型： | CCFL 控制器 |
| 频率： | 175 ~ 225 kHz |
| 电流 - 电源： | 6mA |
| 电源电压： | 3 V ~ 6.5 V |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
LT1186F
PI N FU N CTIO N S
BAT (Pin 14): This pin connects to the battery or AC wall
adapter voltage from which the CCFL Royer converter
operates. This voltage is typically higher than the V CC
supply voltage but can equal V CC if V CC is a 5V logic supply.
The BAT voltage must be at least 2.1V greater than the
internal 2.4V regulator or 4.5V. This pin provides biasing
for the lamp-current programming block, is used with the
Royer pin for floating-lamp configurations and connects
to one input for the open-lamp protection circuitry. For
floating-lamp configurations, this pin is the noninverting
terminal of a high-side current sense amplifier. The typical
quiescent current is 50 μ A into the pin. The BAT and Royer
pins monitor the primary-side Royer converter current
through an internal 0.1 ? topside current sense resistor. A
0A to1A primary-side, center tap converter current is
translated to an input signal range of 0mV to 100mV for the
current sense amplifier. This input range translates to a
0 μ A to 500 μ A sink current at the CCFL V C pin that nulls
against the source current provided by the programmer
circuit. The BAT pin also connects to the topside of the
internal clamp between the BAT and BULB pins that is used
for open-lamp protection.
BULB (Pin 15): This pin connects to the low side of a 7V
threshold comparator between the BAT and BULB pins.
This circuit sets the maximum voltage level across the
primary side of the Royer converter under all operating
TEST CIRCUITS
conditions and limits the maximum secondary output
under start-up conditions or open-lamp conditions. This
eases transformer voltage rating requirements. Set the
voltage limit to ensure lamp start-up with worst-case,
lamp start voltages and cold temperature, system operat-
ing conditions. The BULB pin connects to the junction of
an external divider network. The divider network connects
from the center tap of the Royer transformer or the actual
battery supply voltage to the topside of the current source
“tail inductor.” A capacitor across the top of the divider
network filters switching ripple and sets a time constant
that determines how quickly the clamp activates. When
the comparator activates, sink current is generated to pull
the CCFL V C pin down. This action transfers the entire
regulator loop from current mode operation into voltage
mode operation.
CCFL V SW (Pin 16): This pin is the collector of the internal
NPN power switch for the CCFL regulator. The power
switch provides a minimum of 1.25A. Maximum switch
current is a function of duty cycle as internal slope com-
pensation ensures stability with duty cycles greater than
50%. Using a driver loop to automatically adapt base drive
current to the minimum required to keep the switch in a
quasi-saturation state yields fast switching times and high
efficiency operation. The ratio of switch current to driver
current is about 50:1.
Load Circuit for t DO
Voltage Waveforms for t DO
Voltage Waveforms for t DZ , t DV
1.4V
3k
CLK
0.8V
CS
0.8V
2.0V
D OUT
100pF
D OUT
t DO
2.4V
D OUT
WAVEFORM 1
2.4V
90%
0.4V
(SEE NOTE 1)
LT1186F ? TC01
LT1186F ? TC03
t DV
t DZ
D OUT
(SEE NOTE 2)
Load Circuit for t DZ , t DV
WAVEFORM 2
0.4V
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL
CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS
DISABLED BY CS
10%
D OUT
3k
100pF
5V t DZ WAVEFORM 2, t DV
t DZ WAVEFORM 1
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL
CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS
DISABLED BY CS
LT1186F ? TC04
LT1186F ? TC02
9
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