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| 型号： | LT1339CSW#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 15/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST PWM CM 20-SOIC |
| 标准包装： | 1,000 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 150kHz |
| 占空比： | 90% |
| 电源电压： | 最高 60V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 包装： | 带卷 (TR) |
LT1339
APPLICATIO N S I N FOR M ATIO N
( I MAX ) ( V OUT ( V IN – V OUT ) )
Inhighvoltageapplications(V IN >20V),thetopsideswitch
is required to slew very large voltages. As V IN increases,
transition losses increase through a square relation, until
it becomes the dominant power loss term in the main
switch. This transition loss takes the form:
P TR ≈ (k)(V IN ) 2 (I MAX )(C RSS )(f O )
where k is a constant inversely related to the gate drive
current, approximated by k = 2 in LT1339 applications.
The maximum power loss terms for the switches are thus:
P MAIN = (DC)(I MAX ) 2 (1 + δ )(R DS(ON) ) +
2(V IN ) 2 (I MAX )(C RSS )(f O )
P SYNC = (1 – DC)(I MAX ) 2 (1 + δ )(R DS(ON) )
The (1 + δ ) term in the above relations is the temperature
dependency of R DS(ON) , typically given in the form of a
normalized R DS(ON) vs Temperature curve in a MOSFET
data sheet.
In some applications, parasitic FET capacitances couple
the negative going switch node transient onto the bottom
gate drive pin of the LT1339, causing a negative voltage in
excess of the Absolute Maximum Rating to be imposed on
that pin. Connection of a catch Schottky (rated to about 1A
is typically sufficient) from this pin to ground will eliminate
this effect.
C IN and C OUT Supply Decoupling Capacitor Selection
The large currents typical of LT1339 applications require
special consideration for the converter input and output
supply decoupling capacitors. Under normal steady state
operation, the source current of the main switch MOSFET
is a square wave of duty cycle V OUT /V IN . Most of this
current is provided by the input bypass capacitor. To
prevent large input voltage transients and avoid bypass
capacitor heating, a low ESR input capacitor sized for the
maximum RMS current must be used. This maximum
capacitor RMS current follows the relation:
1 / 2
I RMS ≈
V IN
which peaks at a 50% duty cycle, when I RMS = I MAX /2.
Capacitor ripple current ratings are often based on only
2000 hours (three months) lifetime; it is advisable to
derate either the ESR or temperature rating of the capaci-
tor for increased MTBF of the regulator.
The output capacitor in a buck converter generally has
much less ripple current than the input capacitor. Peak-to-
peak ripple current is equal to that in the inductor ( ? I L ),
typically a fraction of the load current. C OUT is selected to
reduce output voltage ripple to a desirable value given an
expected output ripple current. Output ripple ( ? V OUT ) is
approximated by:
? V OUT ≈ ? I L {ESR + [(4)(f O ) ? C OUT ] –1 }
where f O = operating frequency.
Efficiency Considerations and Heat Dissipation
High output power applications have inherent concerns
regarding power dissipation in converter components.
Although high efficiencies are achieved using the LT1339,
the power dissipated in the converter climbs to relatively
high values when the load draws large amounts of power.
Even at 90% efficiency, an application that provides 500W
to the load has conversion loss of 55W.
I 2 R dissipation through the switches, sense resistor and
inductor series resistance create substantial losses under
high currents. Generally, the dominant I 2 R loss is evident
in the FET switches. Loss in each switch is proportional to
the conduction time of that switch. For example, in a 48V
to 5V converter the synchronous FET conducts load cur-
rent for almost 90% of the cycle time and thus, requires
greater consideration for dissipating I 2 R power.
Gate charge/discharge current creates additional current
drain on the 12V supply. If powered from a high voltage
input through a linear regulator, the losses in that regula-
tor device can become significant. A supply solution
bootstrapped from the output would draw current from a
lower voltage source and reduce this loss component.
Transition losses are significant in the topside switch FET
when high V IN voltages are used. Transition losses can be
estimated as:
P TLOSS ≈ 2(V IN ) 2 (I MAX )(C RSS )(f O )
Since the conduction time in the main switch of a 48V to
5V converter is small, the I 2 R loss in the main switch FET
sn1339 1339fas
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相关代理商/技术参数 |
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| LT1339I | 制造商:LINER 制造商全称:Linear Technology 功能描述:High Power Synchronous DC/DC Controller |
| LT1339IN | 功能描述:IC REG CTRLR BST PWM CM 20-DIP RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LT1339IN#PBF | 功能描述:IC REG CTRLR BST PWM CM 20-DIP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LT1339ISW | 功能描述:IC REG CTRLR BST PWM CM 20-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LT1339ISW#PBF | 功能描述:IC REG CTRLR BST PWM CM 20-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 特色产品:LM3753/54 Scalable 2-Phase Synchronous Buck Controllers 标准包装:1 系列:PowerWise® PWM 型:电压模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.5 V ~ 18 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-5°C ~ 125°C 封装/外壳:32-WFQFN 裸露焊盘 包装:Digi-Reel® 产品目录页面:1303 (CN2011-ZH PDF) 其它名称:LM3754SQDKR |
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