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| 型号： | LT1339CSW#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST PWM CM 20-SOIC |
| 标准包装： | 1,000 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 150kHz |
| 占空比： | 90% |
| 电源电压： | 最高 60V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 包装： | 带卷 (TR) |
LT1339
OPERATIO N
(Refer to Functional Block Diagram)
The current comparator trip threshold is set on the V C pin,
which is the output of a transconductance amplifier, or
error amplifier (EA). The error amplifier integrates the
difference between a feedback voltage (on the V FB pin)
and an internal bandgap generated reference voltage of
1.25V, forming a signal that represents required load
current. If the supplied current is insufficient for a given
load, the output will droop, thus reducing the feedback
voltage. The error amplifier forces current out of the V C
pin, increasing the current comparator threshold. Thus,
the circuit will servo until the provided current is equal to
the required load and the average output voltage is at the
value programmed by the feedback resistors.
Average Current Limit
The output of the sense amplifier is monitored by a single
pole integrator comprised of an external capacitor on the
I AVG pin and an internal impedance of approximately
50k ? . If this averaged value signal exceeds a level corre-
sponding to 120mV across the external sense resistor, the
current comparator threshold is clamped and cannot
continue to rise in response to the error amplifier. Thus, if
average load current requirements exceed 120mV/R SENSE ,
the supply will current limit and the output voltage will fall
out of regulation. The average current limit circuit moni-
tors the sense amplifier output without slope compensa-
tion or ripple current contributions, therefore the average
load current limit threshold is unaffected by duty cycle.
Undervoltage Lockout
The LT1339 employs an undervoltage lockout circuit
(UVLO) that monitors the 12V supply rail. This circuit
disables the output drive capability of the LT1339 if
the 12V supply drops below about 9V. Unstable mode
switching is prevented through 350mV of UVLO threshold
hysteresis.
Adaptive Nonoverlapping Output Stage
The FET driver output stage implements adaptive
nonoverlapping control. This circuitry maintains dead
time independent of the type, size or operating conditions
of the switch elements. The control circuit monitors the
output gate drive signals, insuring that the switch gate
(being disabled) is fully discharged before enabling the
other switch driver.
Shutdown
The LT1339 can be put into low current shutdown mode
by pulling the RUN/SHDN pin low, disabling all circuit
functions. The shutdown threshold is a bandgap referred
voltage of 1.25V typical. Use of a precision threshold on
the shutdown circuit enables use of this pin for undervolt-
age protection of the V IN supply and/or power supply
sequencing.
Soft Start
The LT1339 incorporates a soft start function that oper-
ates by slowly increasing the internal current limit. This
limit is controlled by clamping the V C node to a low voltage
that climbs with time as an external capacitor on the SS pin
is charged with about 8 μ A. This forces a graceful climb of
output current capability, and thus a graceful increase in
output voltage until steady-state regulation is achieved.
The soft start timing capacitor is clamped to ground
during shutdown and during undervoltage lockout, yield-
ing a graceful output recovery from either condition.
5V Internal Reference
Power for the oscillator timing elements and most other
internal LT1339 circuits is derived from an internal 5V
reference, accessible at the 5V REF pin. This supply pin can be
loaded with up to 10mA DC (20mA pulsed) for convenient
biasing of local elements such as control logic, etc.
Slope Compensation
For duty cycles greater than 50%, slope compensation is
required to prevent current mode duty cycle instability in
the regulator control loop. The LT1339 employs internal
slope compensation that is adequate for most applica-
tions. However, if additional slope compensation is
desired, it is available through the SL/ADJ pin. Excessive
slope compensation will cause reduction in maximum
load current capability and therefore is not desirable.
sn1339 1339fas
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相关代理商/技术参数 |
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| LT1339I | 制造商:LINER 制造商全称:Linear Technology 功能描述:High Power Synchronous DC/DC Controller |
| LT1339IN | 功能描述:IC REG CTRLR BST PWM CM 20-DIP RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LT1339IN#PBF | 功能描述:IC REG CTRLR BST PWM CM 20-DIP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LT1339ISW | 功能描述:IC REG CTRLR BST PWM CM 20-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LT1339ISW#PBF | 功能描述:IC REG CTRLR BST PWM CM 20-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 特色产品:LM3753/54 Scalable 2-Phase Synchronous Buck Controllers 标准包装:1 系列:PowerWise® PWM 型:电压模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.5 V ~ 18 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-5°C ~ 125°C 封装/外壳:32-WFQFN 裸露焊盘 包装:Digi-Reel® 产品目录页面:1303 (CN2011-ZH PDF) 其它名称:LM3754SQDKR |
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