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| 型号： | LT1506CR#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 19/24页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 4.5A D2PAK |
| 标准包装： | 750 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调 |
| 输入电压： | 4 V ~ 15 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 500kHz |
| 电流 - 输出： | 4.5A |
| 同步整流器： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-263-8，D²Pak（7 引线+接片），TO-263CA |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | D2PAK-7 |
LT1506
APPLICATIO N S I N FOR M ATIO N
40
V IN = 10V
40
3000
200
20
GAIN
V OUT = 5V
I OUT = 2A
0
2500
PHASE
150
2000
GAIN
100
0
PHASE
–40
1500
V FB ( 2 × 10 –3 )
R OUT
200k
V C
C OUT
12pF
50
–20
–80
1000
ERROR AMPLIFIER EQUIVALENT CIRCUIT
0
R LOAD = 50 ?
–40
10
100
1k 10k
100k
–120
1M
500
100
1k
10k 100k
1M
–50
10M
FREQUENCY (Hz)
1505 F10
Figure 10. Response from V C Pin to Output
FREQUENCY (Hz)
1506 F11
Figure 11. Error Amplifier Gain and Phase
Error amplifier transconductance phase and gain are shown
in Figure 11. The error amplifier can be modeled as a
transconductance of 2000 μ Mho, with an output imped-
ance of 200k ? in parallel with 12pF. In all practical
applications, the compensation network from V C pin to
ground has a much lower impedance than the output
impedance of the amplifier at frequencies above 500Hz.
80
60
40
20
GAIN
PHASE
200
150
100
50
This means that the error amplifier characteristics them-
selves do not contribute excess phase shift to the loop, and
the phase/gain characteristics of the error amplifier sec-
tion are completely controlled by the external compensa-
0
–20
10
V IN = 10V
V OUT = 5V, I OUT = 2A
C OUT = 100 μ F, 10V, AVX TPS
C C = 1.5nF, R C = 0, L = 10 μ H
100 1k 10k
100k
0
–50
1M
tion network.
FREQUENCY (Hz)
1505 F12
) ( )( )( )( )
(
R C Loop Gain = 1 =
V
In Figure 12, full loop phase/gain characteristics are
shown with a compensation capacitor of 1.5nF, giving the
error amplifier a pole at 530Hz, with phase rolling off to 90 °
and staying there. The overall loop has a gain of 74dB at
low frequency, rolling off to unity-gain at 100kHz. Phase
shows a two-pole characteristic until the ESR of the output
capacitor brings it back above 10kHz. Phase margin is
about 60 ° at unity-gain.
Analog experts will note that around 4.4kHz, phase dips
very close to the zero phase margin line. This is typical of
switching regulators, especially those that operate over a
wide range of loads. This region of low phase is not a
problem as long as it does not occur near unity-gain. In
practice, the variability of output capacitor ESR tends to
dominate all other effects with respect to loop response.
Variations in ESR will cause unity-gain to move around,
but at the same time phase moves with it so that adequate
phase margin is maintained over a very wide range of ESR
( ≥ ± 3:1).
Figure 12. Overall Loop Characteristics
What About a Resistor in the Compensation Network?
It is common practice in switching regulator design to add
a “zero” to the error amplifier compensation to increase
loop phase margin. This zero is created in the external
network in the form of a resistor (R C ) in series with the
compensation capacitor. Increasing the size of this resis-
tor generally creates better and better loop stability, but
there are two limitations on its value. First, the combina-
tion of output capacitor ESR and a large value for R C may
cause loop gain to stop rolling off altogether, creating a
gain margin problem. An approximate formula for R C
where gain margin falls to zero is:
OUT
G MP G MA ESR 2 . 42
19
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| LT1506CS8#PBF | 功能描述:IC REG BUCK ADJ 4.5A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:250 系列:- 类型:降压（降压） 输出类型:固定 输出数:1 输出电压:1.2V 输入电压:2.05 V ~ 6 V PWM 型:电压模式 频率 - 开关:2MHz 电流 - 输出:500mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:6-UFDFN 包装:带卷 (TR) 供应商设备封装:6-SON（1.45x1） 产品目录页面:1032 (CN2011-ZH PDF) 其它名称:296-25628-2 |
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