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| 型号： | LT1533IS#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/20页 |
| 文件大小： | 0K |
| 描述： | IC REG PUSH-PLL CTRLR ISO 16SOIC |
| 标准包装： | 50 |
| 类型： | 推挽式控制器，隔离式 |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.3 V ~ 30 V |
| 输入电压： | 2.7 V ~ 23 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz ~ 250kHz |
| 电流 - 输出： | 1A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
| 供应商设备封装： | 16-SOIC |
| 产品目录页面： | 1327 (CN2011-ZH PDF) |
LT1533
APPLICATIO N S I N FOR M ATIO N
Thermal Considerations
Computing power dissipation for this IC requires careful
attention to detail. Reduced output slewing causes the part
to dissipate more power than would occur with fast edges.
However, much improvement in noise can be produced
with modest decrease in supply efficiency.
Power dissipation is a function of topology, input voltage,
switch current and slew rates. It is impractical to come up
with an all-encompassing formula. It is therefore recom-
mended that package temperature be measured in each
application. The part has an internal thermal shutdown to
prevent device destruction, but this should not replace
careful thermal design.
1. Dissipation due to input current:
where ? I is the ripple current in the switch, R CSL and
R VSL are the slew resistors and f OSC is the oscillator
frequency.
Power dissipation P D is the sum of these three terms. Die
junction temperature is then computed as:
T J = T AMB + (P D )( θ JA )
where T AMB is ambient temperature and θ JA is the package
thermal resistance. For the 16-pin SO θ JA is 100 ° C/W.
For example, with f OSC = 40kHz, V IN = 10V, 0.4A average
current and 0.1A of ripple, the maximum duty cycle is
44%. Assume slew resistors are both 17k and V SAT is
0.26V, then:
P D = 0.176W + 0.094W + 0.158W = 0.429W
P VIN IN ? 11 mA +
= V
?
?
I ?
60 ? ?
In an S16 package the die junction temperature would be
43 ° C above ambient.
?
2 ?
()
( )
? V I 2 + ? I
?
I ? V IN ? SAT ?
? IN ??
?
?
4 ?
4 ? ?
( ) ( ) ( )
P SLEW = ?
R VSL ? f OSC
R CSL +
( ) ( )
33 10 9 ?
220 10 9 ?
?? ??
( 1 . 25 )( V RIPPLE )( g m )( R VC )
()( ) ( )(
) ( )( )()
P SLEW = ?
? I R CSL V IN R VSL ?
? f OSC IN I
( )
( )
? 33 ? ? 10 ? ?
220 10 9 ? ?
?
where I is the average switch current.
2. Dissipation due to the drivers saturation:
P VSAT = (V SAT )(I)(DC MAX )
where V SAT is the output saturation voltage which is
approximately 0.1 + (0.4)(I), DC MAX is the maximum
duty cycle.
3. Dissipation due to output slew using approximations
for slew rates:
? ? 2 ? ?
2 V
?
? ? ?
? ? ? ?
? ? ? ? ? ?
? ?
Note if V SAT and ? I are small with respect to V IN and I,
then:
? ?
+ V
9
? ? ? ?
10
Frequency Compensation
Loop frequency compensation is accomplished by way of
a series RC network on the output of the error amplifier (V C
pin). Referring to Figure 3, the main pole is formed by
capacitor C VC and the output impedance of the error
amplifier (approximately 400k ? ). The series resistor R VC
creates a “zero” which improves loop stability and tran-
sient response. A second capacitor C VC2 , typically one-
tenth the size of the main compensation capacitor, is
sometimes used to reduce the switching frequency ripple
on the V C pin. V C pin ripple is caused by output voltage
ripple attenuated by the output divider and multiplied by
the error amplifier. Without the second capacitor, V C pin
ripple is:
V C PIN RIPPLE =
V OUT
where V RIPPLE = Output ripple (V P-P )
g m = Error amplifier transconductance
R VC = Series resistor on V C pin
V OUT = DC output voltage
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