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参数资料
| 型号： | LT1533IS#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC REG PUSH-PLL CTRLR ISO 16SOIC |
| 标准包装： | 50 |
| 类型： | 推挽式控制器，隔离式 |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.3 V ~ 30 V |
| 输入电压： | 2.7 V ~ 23 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz ~ 250kHz |
| 电流 - 输出： | 1A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
| 供应商设备封装： | 16-SOIC |
| 产品目录页面： | 1327 (CN2011-ZH PDF) |
LT1533
APPLICATIO N S I N FOR M ATIO N
V OUT ? 2 . 5 ?
? 2 . 5 + R 2 ? 25 μ A ?
slower slewing waveforms will dissipate more power so
that efficiency will drop. You can also monitor this as you
make your slew adjustment by measuring input and out-
put voltage and current.
It is possible to use a single slew setting resistor. In this
case the R VSL and R CSL pins are tied together. A resistor
with a value of 2k to 34k (one half the individual resistors)
can then be tied from these pins to ground.
Emitter Inductance
A small inductance in the power ground minimizes a
potential dip in the output current falling edge that can
occur under fast slewing, 25nH is usually sufficient. Greater
than 50nH may produce unwanted oscillations in the
voltage output. The inductance can be created by wire or
internal regulator voltage (2.4V typ), output regulation
may be disrupted. A series resistance with the feedback
pin can eliminate this potential problem.
Negative Output Voltage Setting
Negative output voltage can be sensed using the NFB pin.
In this case regulation will occur when the NFB pin is at
– 2.5V. The input bias current for the NFB is –25 μ A (I NFB )
which needs to be accounted for in setting up the divider.
Referring to Figure 2, R1 is chosen such that:
?
R 1 = R 2 ? ?
? ?
board trace with the equivalent of one inch of straight
length. A spiral board trace will require less length.
NFB PIN
I NFB
R2
R1
–V OUT
Positive Output Voltage Setting
1533 F02
Sensing of a positive output voltage is usually done using
a resistor divider from the output to the FB pin. The
positive input to the error amp is connected internally to a
1.25V bandgap reference. The FB pin will regulate to this
voltage.
Figure 2
A suggested value for R2 is 2.5k. The NFB pin is normally
left open if the FB pin is being used.
FB PIN
R1
V OUT
Dual Polarity Output Voltage Sensing
R 1 = R 2 ? OUT ? 1 ?
R2
1533 F01
Figure 1
Referring to Figure 1, R1 is determined by:
? V ?
? 1 . 25 ?
The FB bias current represents a small error and can
usually be ignored for values of R1 || R2 up to 10k.
One word of caution. Sometimes a feedback zero is added
to the control loop by placing a capacitor across R1 above.
Certain applications may benefit from sensing both posi-
tive and negative output voltages. When doing this each
output voltage resistor divider is individually set as previ-
ously described. When both FB and NFB pins are used, the
LT1533 will act to prevent either output from going
beyond its set output voltage. The highest output (lightest
load) will dominate control of the regulator. This technique
would prevent either output from going unregulated high
at no load. However, this technique will also compromise
output load regulation.
Shutdown
If the shutdown pin is pulled low, the regulator will turn off.
The supply current will be reduced to less than 20 μ A.
If the feedback capacitively pulls the FB pin above the
9
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