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| 型号： | LT1578IS8#TR |
| 厂商： | Linear Technology |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 1.5A 8SOIC |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 1.21V |
| 输入电压： | 4 V ~ 15 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 8-SOIC |
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LT1578/LT1578-2.5
APPLICATIO N S I N FOR M ATIO N
[ ( ) ]
2 . 42 ? 25 k ( )
25 k ( )
(
)
R LO ( IN ? 2 . 42 V )
(
)
[ ( ) ]
(
)
conditions. UVLO helps prevent the regulator from oper-
ating at source voltages where these problems might
occur.
Threshold voltage for lockout is about 2.42V. A 3.5 μ A bias
current flows out of the pin at threshold. This internally
generated current is used to force a default high state on
the shutdown pin if the pin is left open. When low shut-
down current is not an issue, the error due to this current
can be minimized by making R LO 10k or less. If shutdown
current is an issue, R LO can be raised to 100k, but the error
due to initial bias current and changes with temperature
should be considered.
R LO = 10 k to 100k ( 25k suggested )
V
R HI =
2 . 42 V ? R LO 3 . 5 μ A
V IN = Minimum input voltage
Keep the connections from the resistors to the shutdown
pin short and make sure that interplane or surface capaci-
tance to the switching nodes are minimized. If high resis-
tor values are used, the shutdown pin should be bypassed
with a 1000pF capacitor to prevent coupling problems
from the switch node. If hysteresis is desired in the
undervoltage lockout point, a resistor R FB can be added to
the output node. Resistor values can be calculated from:
R LO V IN ? 2 . 42 ? V / V OUT + 1 + ? V
R HI =
2 . 42 ? R LO 3 . 5 μ A
R FB = ( R HI )( V OUT / ? V )
25k suggested for R LO
V IN = Input voltage at which switching stops as input
voltage descends to trip level
? V = Hysteresis in input voltage level
Example: output voltage is 5V, switching is to stop if input
input rises back to 13.5V. ? V is therefore 1.5V and
V IN = 12V. Let R LO = 25k.
25 k 12 ? 2 . 42 1 . 5 / 5 + 1 + 1 . 5
R HI =
3 . 5 μ A
10 . 35
= = 111 k
2 . 33
R FB = 111 k 5 / 1 . 5 = 370 k
SWITCH NODE CONSIDERATIONS
For maximum efficiency, switch rise and fall times are
made as short as possible. To prevent radiated EMI and
high frequency resonance problems, proper layout of the
components connected to the switch node is essential. B
field (magnetic) radiation is minimized by keeping catch
diode, switch pin, and input bypass capacitor leads as
short as possible. E field radiation is kept low by minimiz-
ing the length and area of all traces connected to the switch
pin and BOOST pin. A ground plane should always be used
under the switcher circuitry to prevent interplane cou-
pling. A suggested layout for the critical components is
shown in Figure 5. Note that the feedback resistors and
compensation components are kept as far as possible
from the switch node. Also note that the high current
ground path of the catch diode and input capacitor are kept
very short and separate from the analog ground line.
The high speed switching current path is shown schemati-
cally in Figure 6. Minimum lead length in this path is
essential to ensure clean switching and low EMI. The path
including the switch, catch diode, and input capacitor is
the only one containing nanosecond rise and fall times. If
you follow this path on the PC layout, you will see that it is
irreducibly short. If you move the diode or input capacitor
away from the LT1578, get your resumé in order. The
other paths contain only some combination of DC and
200kHz triwave, so are much less critical.
voltage drops below 12V and should not restart unless
15
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