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参数资料
| 型号： | LT1611CS5#TR |
| 厂商： | Linear Technology |
| 文件页数： | 5/12页 |
| 文件大小： | 0K |
| 描述： | IC REG INV ADJ 0.3A SOT23-5 |
| 标准包装： | 2,500 |
| 类型： | 反相 |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | -0.9 V ~ -10 V |
| 输入电压： | 0.9 V ~ 10 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.4MHz |
| 电流 - 输出： | 300mA |
| 同步整流器： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SC-74A，SOT-753 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | SOT-23-5 |
LT1611
OPERATIO
boost converter, generating a negative output voltage,
which is directly regulated. The circuit schematic is de-
tailed in Figure 3. Only one inductor is required, and the
two diodes can be in a single SOT-23 package. Output
noise is the same as in a boost converter, because current
is delivered to the output only during the time when the
LT1611’s internal switch is off.
If D2 is replaced by an inductor, as shown in Figure 4, a
higher performance solution results. This converter topol-
ogy was developed by Professor S. Cuk of the California
Institute of Technology in the 1970s. A low ripple voltage
results with this topology due to inductor L2 in series with
the output. Abrupt changes in output capacitor current are
eliminated because the output inductor delivers current to
the output during both the off-time and the on-time of the
LT1611 switch. With proper layout and high quality output
capacitors, output ripple can be as low as 1mV P–P .
The operation of Cuk’s topology is shown in Figures 5
and 6. During the first switching phase, the LT1611’s
switch, represented by Q1, is on. There are two current
loops in operation. The first loop begins at input capacitor
C1, flows through L1, Q1 and back to C1. The second loop
flows from output capacitor C3, through L2, C2, Q1 and
back to C3. The output current from R LOAD is supplied by
L2 and C3. The voltage at node SW is V CESAT and at node
SWX the voltage is –(V IN + |V OUT |). Q1 must conduct both
L1 and L2 current. C2 functions as a voltage level shifter,
with an approximately constant voltage of (V IN + |V OUT |)
across it.
When Q1 turns off during the second phase of switching,
the SW node voltage abruptly increases to (V IN + |V OUT |).
The SWX node voltage increases to V D (about 350mV).
Now current in the first loop, begining at C1, flows through
L1, C2, D1 and back to C1. Current in the second loop flows
from C3 through L2, D1 and back to C3. Load current
continues to be supplied by L2 and C3.
An important layout issue arises due to the chopped
nature of the currents flowing in Q1 and D1. If they are both
tied directly to the ground plane before being combined,
switching noise will be introduced into the ground plane.
It is almost impossible to get rid of this noise, once present
in the ground plane. The solution is to tie D1’s cathode to
the ground pin of the LT1611 before the combined cur-
rents are dumped into the ground plane as drawn in
Figures 4, 5 and 6. This single layout technique can
virtually eliminate high frequency “spike” noise so often
present on switching regulator outputs.
Output ripple voltage appears as a triangular waveform
riding on V OUT . Ripple magnitude equals the ripple current
of L2 multiplied by the equivalent series resistance (ESR)
of output capacitor C3. Increasing the inductance of L1
and L2 lowers the ripple current, which leads to lower
output voltage ripple. Decreasing the ESR of C3, by using
ceramic or other low ESR type capacitors, lowers output
ripple voltage. Output ripple voltage can be reduced to
arbitrarily low levels by using large value inductors and
low ESR, high value capacitors.
L1
C2
1 μ F
D2
L1
C2
1 μ F
L2
V IN
V IN
+
C1
V IN
SW
D1
–V OUT
+
C1
V IN
SW
D1
–V OUT
LT1611
R1
LT1611
R1
SHUTDOWN
SHDN
GND
NFB
R2
C3
GND
NFB
R2
C3
10k
Figure 3. Direct Regulation of Negative Output
Using Boost Converter with Charge Pump
1611 F03
10k
1611 F04
Figure 4. L2 Replaces D2 to Make Low Output Ripple
Inverting Topology. Coupled or Uncoupled Inductors Can
Be Used. Follow Phasing If Coupled for Best Results
5
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