参数资料
型号: LT1611CS5#TR
厂商: Linear Technology
文件页数: 8/12页
文件大小: 0K
描述: IC REG INV ADJ 0.3A SOT23-5
标准包装: 2,500
类型: 反相
输出类型: 可调式
输出数: 1
输出电压: -0.9 V ~ -10 V
输入电压: 0.9 V ~ 10 V
PWM 型: 电流模式
频率 - 开关: 1.4MHz
电流 - 输出: 300mA
同步整流器:
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: SC-74A,SOT-753
包装: 带卷 (TR)
供应商设备封装: SOT-23-5
LT1611
OPERATIO
In Figure 11 (also shown on the first page), output capaci-
tor C3 is replaced by a ceramic unit. These large value
ceramic capacitors have ESR of about 2m ? and result in
very low output ripple. At the 20mV/division scale, output
voltage ripple cannot be seen. Figure 12 pictures the
output and switch nodes at 200ns per division. The output
voltage ripple is approximately 1mV P–P . Again, good
layout is mandatory to achieve this level of performance.
Layout
The LT1611 switches current at high speed, mandating
careful attention to layout for best performance. You will
not get advertised performance with careless layout. Figure 13
shows recommended component placement. Follow this
closely in your printed circuit layout. The cut ground
copper at D1’s cathode is essential to obtain the low noise
achieved in Figures 11 and 12’s oscillographs. Input
bypass capacitor C1 should be placed close to the LT1611
as shown. The load should connect directly to output
capacitor C2 for best load regulation. You can tie the local
ground into the system ground plane at C3’s ground
terminal.
V OUT
5mV/DIV
AC COUPLED
V OUT
20mV/DIV
AC COUPLED
SWITCH VOLTAGE
LOAD CURRENT
150mA
50mA
5V/DIV
100 μ s/DIV
1611 F11
LOAD = 150mA
200ns/DIV
1611 F12
Figure 11. Replacing C3 with 22 μ F Ceramic Capacitor
(Taiyo Yuden JMK325BJ226MM) Improves Output
Noise. C PL = 1200pF Results in Best Phase Margin
L1B
L1A
Figure 12. 22 μ F Ceramic Capacitor at
Output Reduces Ripple to 1mV P–P . Proper
Layout Is Essential to Achieve Low Noise
–V OUT
C1
+
C3
D1
C2
V IN
1
2
5
GND
R2
3
R1
4
SHUTDOWN
1611 F13
Figure 13. Suggested Component Placement. Note Cut in Ground Copper at D1’s Cathode
8
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