参数资料
型号: LT1676IS8#TRPBF
厂商: Linear Technology
文件页数: 6/16页
文件大小: 0K
描述: IC REG BUCK ADJ 0.7A 8SOIC
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.24 V ~ 51 V
输入电压: 7.4 V ~ 60 V
PWM 型: 电流模式,混合
频率 - 开关: 100kHz
电流 - 输出: 700mA
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
供应商设备封装: 8-SOIC
LT1676
BLOCK DIAGRA
V CC 2
V BG
R1
R SENSE
5
V IN
SHDN 1
BIAS
V B
SWDR
SWDR
I
COMP
Q4
Q3
Q2
SYNC 6
OSC
LOGIC
SWON
BOOST
SWOFF
Q1
3
V SW
D1
GND 4
BOOST
COMP
SWON
I
V C 8
I
I
FB 7
FB
AMP
V TH
BOOST
gm
I
SWOFF
Q5
V BG
1676 BD
OPERATIO
The LT1676 is a current mode switching regulator IC that
has been optimized for high efficiency operation in high
input voltage, low output voltage Buck topologies. The
Block Diagram shows an overall view of the system.
Several of the blocks are straightforward and similar to
those found in traditional designs, including: Internal Bias
Regulator, Oscillator and Feedback Amplifier. The novel
portion includes an elaborate Output Switch section and
Logic Section to provide the control signals required by
the switch section.
The LT1676 operates much the same as traditional
current mode switchers, the major difference being its
specialized output switch section. Due to space con-
straints, this discussion will not reiterate the basics of
current mode switcher/controllers and the “Buck” topol-
ogy. A good source of information on these topics is
Application Note 19.
Output Switch Theory
One of the classic problems in delivering low output
voltage from high input voltage at good efficiency is that
minimizing AC switching losses requires very fast volt-
age (dV/dt) and current (dI/dt) transition at the output
device. This is in spite of the fact that in a bipolar
implementation, slow lateral PNPs must be included in
the switching signal path.
Fast positive-going slew rate action is provided by lateral
PNP Q3 driving the Darlington arrangement of Q1 and Q2.
The extra β available from Q2 greatly reduces the drive
requirements of Q3.
Although desirable for dynamic reasons, this topology
alone will yield a large DC forward voltage drop. A second
lateral PNP, Q4, acts directly on the base of Q1 to reduce
the voltage drop after the slewing phase has taken place.
To achieve the desired high slew rate, PNPs Q3 and Q4 are
“force-fed” packets of charge via the current sources
controlled by the boost signal.
6
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