参数资料
型号: LT1765ES8
厂商: Linear Technology
文件页数: 11/20页
文件大小: 0K
描述: IC REG BUCK ADJ 3A 8SOIC
标准包装: 100
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.2 V ~ 20 V
输入电压: 3 V ~ 25 V
PWM 型: 电流模式
频率 - 开关: 1.25MHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 管件
供应商设备封装: 8-SOIC
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
An internal comparator will force the part into shutdown
below the minimum V IN of 2.6V. This feature can be used
to prevent excessive discharge of battery-operated sys-
tems. If an adjustable UVLO threshold is required, the
shutdown pin can be used. The threshold voltage of the
shutdown pin comparator is 1.33V. A 3μA internal current
source defaults the open pin condition to be operating (see
Typical Performance Graphs). Current hysteresis is added
above the SHDN threshold. This can be used to set voltage
hysteresis of the UVLO using the following:
threshold with a duty cycle between 20% and 80%. The
input can be driven directly from a logic level output. The
synchronizing range is equal to initial operating frequency
up to 2MHz. This means that minimum practical sync
frequency is equal to the worst-case high self-oscillating
frequency (1.6MHz), not the typical operating frequency
of 1.25MHz. Caution should be used when synchronizing
above 1.8MHz because at higher sync frequencies the
amplitude of the internal slope compensation used to
prevent subharmonic switching is reduced. This type of
R 1 =
R 2 =
V H ? V L
7 μ A
1 . 33 V
( V H ? 1. 33 V ) + 3 μ A
R 1
subharmonic switching only occurs at input voltages less
than twice output voltage. Higher inductor values will tend
to eliminate this problem. See Frequency Compensation
section for a discussion of an entirely different cause of
subharmonic switching before assuming that the cause is
insuf?cient slope compensation. Application Note 19 has
more details on the theory of slope compensation.
V H – Turn-on threshold
V L – Turn-off threshold
Example: switching should not start until the input is above
4.75V and is to stop if the input falls below 3.75V.
V H = 4.75V
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
ef?ciency, switch rise and fall times are typically in the
R 1 =
V L = 3.75V
4. 75V ? 3 .75V
7 μ A
= 143 k
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. Shortening
this path will also reduce the parasitic trace inductance
R 2 =
1 . 33 V
( 4. 75V ? 1. 33V ) + 3 μ A
143 k
= 49 . 4 k
of approximately 25nH/inch. At switch off, this parasitic
inductance produces a ?yback spike across the LT1765
switch. When operating at higher currents and input volt-
ages, with poor layout, this spike can generate voltages
Keep the connections from the resistors to the SHDN
pin short and make sure that the interplane or surface
across the LT1765 that may exceed its absolute maximum
capacitance to the switching nodes are minimized. If high
resistor values are used, the SHDN pin should be bypassed
V IN
LT1765
SW
L1
5V
with a 1nF capacitor to prevent coupling problems from
the switch node.
V IN C3
HIGH
FREQUENCY
CIRCULATING
D1 C1
LOAD
SYNCHRONIZATION
The SYNC pin is used to synchronize the internal oscilla-
tor to an external signal. The SYNC input must pass from
a logic level low, through the maximum synchronization
PATH
Figure 5. High Speed Switching Path
1765 F05
1765fd
11
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