参数资料
型号: LT1765ES8
厂商: Linear Technology
文件页数: 13/20页
文件大小: 0K
描述: IC REG BUCK ADJ 3A 8SOIC
标准包装: 100
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.2 V ~ 20 V
输入电压: 3 V ~ 25 V
PWM 型: 电流模式
频率 - 开关: 1.25MHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 管件
供应商设备封装: 8-SOIC
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
Example: with V IN = 10V, V OUT = 5V and I OUT = 2A:
DIE TEMPERATURE MEASUREMENT
P SW
=
( 0 .13 )( 2 ) ( 2 5 ) +
10
( 17 ? 10 ? 9 ) ( 2 )( 10 ) ( 1 . 25 ? 10 6
)
If a true die temperature is required, a measurement of the
SYNC to GND pin resistance can be used. The SYNC pin
resistance across temperature must ?rst be calibrated, with
( V F ) ( V IN ? V OUT )( I LOAD )
= 0 . 26 + 0 . 43 = 0 . 69 W
P BOOST = ( 5 ) 2 ( 2 / 50 ) = 0 . 1 W
10
P Q = 10 ( 0 . 001 ) = 0 . 01 W
Total power dissipation, P TOT , is 0.69 + 0.1 + 0.01 = 0.8W.
Thermal resistance for the LT1765 16-lead TSSOP exposed
pad package is in?uenced by the presence of internal or
backside planes. With a full plane under the package,
thermal resistance will be about 45°C/W. With no plane
under the package, thermal resistance will increase to
about 110°C/W. For the exposed pad package θ JC(PAD) =
10°C/W. Thermal resistance is dominated by board perfor-
mance. To calculate die temperature, use the appropriate
thermal resistance number and add in worst-case ambient
temperature:
T J = T A + θ JA (PTOT)
When estimating ambient, remember the nearby catch
diode will also be dissipating power.
P DIODE =
V IN
V F = Forward voltage of diode (assume 0.5V at 2A)
no signi?cant output load, in an oven. An initial value of
40k with a temperature coef?cient of 0.16%/°C is typical.
The same measurement can then be used in operation to
indicate the die temperature.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered—the worse
the board layout, the more dif?cult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits, read the ‘LAYOUT CONSIDERATIONS’ section ?rst.
Common layout errors that appear as stability problems
are distant placement of input decoupling capacitor and/or
catch diode, and connecting the V C compensation to a
ground track carrying signi?cant switch current. In addition,
the theoretical analysis considers only ?rst order ideal
component behavior. For these reasons, it is important
that a ?nal stability check is made with production layout
and components.
The LT1765 uses current mode control. This alleviates many
of the phase shift problems associated with the inductor.
The basic regulator loop is shown in Figure 7, with both
tantalum and ceramic capacitor equivalent circuits. The
LT1765 can be considered as two g m blocks, the error
ampli?er and the power stage.
( ) ( )( ) = 0 . 5 W
P DIODE =
0 . 5 10 ? 5 2
10
LT1765
CURRENT MODE
POWER STAGE
V SW
OUTPUT
Notice that the catch diode’s forward voltage contributes
g m = 5mho
ERROR
AMPLIFIER
R1
a signi?cant loss in the overall system ef?ciency. A larger,
FB
TANTALUM
CERAMIC
lower V F diode can improve ef?ciency by several percent.
Typical thermal resistance of the board θ B is 35°C/W. At
an ambient temperature of 25°C,
GND
V C
500k
g m =
850μmho
1.2V
+
ESR
C1
ESL
C1
T J = T A + θ JA (P TOT ) + θ B (P DIODE )
T J = 25 + 45 (0.8) + 35 (0.5) = 79°C
R C
C C
C F
R2
1765 F07
Figure 7. Model for Loop Response
1765fd
13
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