参数资料
型号: LT3071EUFD#TRPBF
厂商: Linear Technology
文件页数: 12/28页
文件大小: 0K
描述: IC REG LDO ADJ 5A 28QFN
标准包装: 2,500
稳压器拓扑结构: 正,可调式
输出电压: 0.8 V ~ 1.8 V
输入电压: 0.95 V ~ 3 V
电压 - 压降(标准): 0.085V @ 5A
稳压器数量: 1
电流 - 输出: 5A
电流 - 限制(最小): 5.1A
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-QFN(4x5)
包装: 带卷 (TR)
LT3071
PIN FUNCTIONS
I MON (Pin 21): Output Current Monitor. The I MON pin
sources a current typically equal to I OUT /2500 or 400μA
per amp of output current. Terminating this pin with a
resistor to GND produces a voltage proportional to I OUT .
For example, at I OUT = 5A, I MON typically sources 2mA.
With a 1k resistor to GND, this produces 2V. If I MON is
unused, tie this pin to V BIAS .
MARGA (Pin 22): Analog Margining. This pin margins the
output voltage over a continuous analog range of ±10%.
Tying this pin to GND adjusts output voltage by –10%.
Driving this pin to 1.2V adjusts output voltage by +10%. A
voltage source or a voltage output DAC is ideal for driving
this pin. If the MARGA function is not used, either float
this pin or terminate with a 1nF capacitor to GND.
V O0 , V O1 and V O2 (Pins 23, 24, 25): Output Voltage Se-
lect. These three-state pins combine to select a nominal
output voltage from 0.8V to 1.8V in increments of 50mV.
Output voltage is limited to 1.8V maximum by an internal
override of V O1 when V O2 = high . The input logic low
threshold is less than 250mV referenced to GND and the
logic high threshold is greater than V BIAS – 250mV. The
range between these two thresholds as set by a window
comparator defines the logic Hi-Z state. See Table 1 in the
Applications Information section that defines the V O2 , V O1
and V O0 settings versus V OUT .
BIAS (Pin 27): Bias Supply. This pin supplies current to
the internal control circuitry and the output stage driving
the pass transistor. The LT3071 requires a minimum 2.2μF
bypass capacitor for stability and proper operation. To
ensure proper operation, the BIAS voltage must satisfy
the following conditions: 2.2V ≤ V BIAS ≤ 3.6V and V BIAS ≥
(1.25 ? V OUT + 1V). For V OUT ≤ 0.95V, the minimum BIAS
voltage is limited to 2.2V.
EN (Pin 28): Enable. This pin enables/disables the output
device only. The internal reference and all support functions
are active if V BIAS is above its UVLO threshold. Pulling EN
low keeps the reference circuit active, but disables the
output pass transistor and puts the LT3071 into a low
power nap mode. The maximum rising EN threshold is
ratioed to 0.56% of V BIAS and the minimum falling ENx
threshold is 0.36% of V BIAS . Drive the EN pin with either
a digital logic port or an open-collector NPN or an open-
drain NMOS terminated with a pull-up resistor to V BIAS .
The pull-up resistor must be less than 35k to meet the V IH
condition of the EN pin. If unused, connect EN to BIAS.
+
V BIAS
EN
BIAS
PWRGD
IN
SENSE
+
V IN
V O0 LT3071
V O1
V O2
MARGA
OUT
I MON
R P
LOAD
VIOC
REF/BYP
GND
R P
3071 F01
Figure 1. Kelvin Sense Connection
3071fb
12
For more information www.linear.com/3071
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