参数资料
| 型号： | LT3071EUFD#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ 5A 28QFN |
| 标准包装： | 2,500 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 0.8 V ~ 1.8 V |
| 输入电压： | 0.95 V ~ 3 V |
| 电压 - 压降（标准）： | 0.085V @ 5A |
| 稳压器数量： | 1 |
| 电流 - 输出： | 5A |
| 电流 - 限制（最小）： | 5.1A |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN（4x5） |
| 包装： | 带卷 (TR) |
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LT3071
APPLICATIONS INFORMATION
REF
SWITCHING REGULATOR
+
PWM
–
IN
LT3071
OUT
LOAD
FB
V OUT +
V REF 300mV
VIOC
REFERENCE
I TH
3071 F02
Figure 2. VIOC Control Block Diagram
PWRGD—Power Good
PWRGD pin is an open-drain NMOS digital output that
actively pulls low if any one of these fault modes is detected:
? V OUT is less than 90% of V OUT(NOMINAL) on the rising
edge of V OUT .
? V OUT drops below 85% of V OUT(NOMINAL) for more than
25μs.
? V BIAS is less than its undervoltage lockout threshold.
? The OUT-to-IN reverse-current detector activates.
? Junction temperature exceeds 145°C typically.*
*The junction temperature detector is an early warning
indicator that trips approximately 20°C before thermal
shutdown engages.
Stability and Output Capacitance
The LT3071’s feedback loop requires an output capacitor
for stability. Choose C OUT carefully and mount it in close
proximity to the LT3071’s OUT and GND pins. Include wide
routing planes for OUT and GND to minimize inductance.
If possible, mount the regulator immediately adjacent to
the application load to minimize distributed inductance for
optimal load transient performance. Point-of-load applica-
tions present the best case layout scenario for extracting
full LT3071 performance.
Low ESR, X5R or X7R ceramic chip capacitors are the
LTC recommended choice for stabilizing the LT3071. Ad-
ditional bulk capacitors distributed beyond the immediate
decoupling capacitors are acceptable as their parasitic ESL
and ESR, combined with the distributed PCB inductance
isolates them from the primary compensation pole provided
by the local surface mount ceramic capacitors.
The LT3071 requires a minimum output capacitance of
15μF for stability. LTC strongly recommends that the output
capacitor network consist of several low value ceramic
capacitors in parallel.
Why Do Multiple, Small-Value Output Capacitors
Connected in Parallel Work Better?
The LT3071’s unity-gain bandwidth with C OUT of 15μF is
about 1MHz at its full-load current of 5A. Surface mounted
MLCC capacitors have a self-resonance frequency of
f R = 1/(2π√ LC ), which must be pushed to a frequency higher
than the regulator bandwidth. Standard MLCC capacitors
are acceptable. To keep the resonant frequency greater
than 1MHz, the product 1/(2π√ LC ) must be greater than
1MHz. At this bandwidth, PCB vias can add significant
inductance, thus the fundamental decoupling capacitors
must be mounted on the same plane as the LT3071.
3071fb
For more information www.linear.com/3071
17
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相关代理商/技术参数 |
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|---|---|
| LT3071IUFD | 制造商:LINER 制造商全称:Linear Technology 功能描述:5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator with Analog Margining |
| LT3071IUFD#PBF | 功能描述:IC REG LDO ADJ 5A 28QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 标准包装:3,000 系列:- 稳压器拓扑结构:正，固定式 输出电压:2.5V 输入电压:2.5 V ~ 5.5 V 电压 - 压降（标准）:- 稳压器数量:1 电流 - 输出:300mA（最小值） 电流 - 限制（最小）:360mA 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SOT-23-5 细型，TSOT-23-5 供应商设备封装:TSOT-23-5 包装:带卷 (TR) |
| LT3071IUFD#TRPBF | 功能描述:IC REG LDO ADJ 5A 28QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 标准包装:3,000 系列:- 稳压器拓扑结构:正，固定式 输出电压:2.5V 输入电压:2.5 V ~ 5.5 V 电压 - 压降（标准）:- 稳压器数量:1 电流 - 输出:300mA（最小值） 电流 - 限制（最小）:360mA 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SOT-23-5 细型，TSOT-23-5 供应商设备封装:TSOT-23-5 包装:带卷 (TR) |
| LT3071IUFD-PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator with Analog Margining |
| LT3071IUFD-TR | 制造商:LINER 制造商全称:Linear Technology 功能描述:5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator with Analog Margining |
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