参数资料
型号: LT3434IFE
厂商: Linear Technology
文件页数: 15/24页
文件大小: 0K
描述: IC REG BUCK ADJ 3A 16TSSOP
标准包装: 95
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.25 V ~ 54 V
输入电压: 3.3 V ~ 60 V
PWM 型: 电流模式,混合
频率 - 开关: 200kHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
供应商设备封装: 16-TSSOP-EP
LT3434
APPLICATIO S I FOR ATIO
? V ? ( I BIASS + I FB + I S )
( η )
I IN ( AVG ) ? I VINS + I SHDN + ? OUT ?
limits the switch current via the V C pin to maintain a
constant voltage ramp rate (dV/dt) at the output capacitor.
A capacitor (C1 in Figure 2) from the C SS pin to the
regulated output voltage determines the output voltage
ramp rate. When the current through the C SS capacitor
exceeds the C SS threshold (I CSS ), the voltage ramp of the
output capacitor is limited by reducing the V C pin voltage.
The C SS threshold is proportional to the FB voltage (see
Typical Performance Characteristics) and is defeated for
FB voltages greater than 0.9V (typical). The output dV/dt
can be approximated by:
average input current is greatly reduced resulting in higher
efficiency.
The minimum average input current depends on the V IN to
V OUT ratio, V C frequency compensation, feedback divider
network and Schottky diode leakage. It can be approxi-
mated by the following equation:
? V IN ?
where
= CSS
dV
dt
I
C SS
I VINS = input pin current in sleep mode
V OUT = output voltage
V IN = input voltage
but actual values will vary due to start-up load conditions,
compensation values and output capacitor selection.
C CSS = 1000pF
C CSS = 0.1 μ F
I BIASS = BIAS pin current in sleep mode
I FB = feedback network current
I S = catch diode reverse leakage at V OUT
η = low current efficiency (non Burst Mode operation)
Example: For V OUT = 3.3V, V IN = 12V
? 3 . 3 ? ( 125 μ A + 12 . 5 μ A + 0 . 5 μ A )
( )
I IN ( AVG ) = 45 μ A + 5 μ A + ? ?
V OUT
0.5V/DIV
C CSS = 0.01 μ F
? 12 ? 0 . 85
= 45 μ A + 5 μ A + 44 μ A = 99 μ A
V IN = 12V
1ms/DIV
3434 F04
150
V OUT = 3.3V
V OUT = 3.3V
I LOAD = 500mA
Figure 4. V OUT dV/dt
125
100
75
Burst Mode OPERATION
To enhance efficiency at light loads, the LT3434 automati-
cally switches to Burst Mode operation which keeps the
50
25
output capacitor charged to the proper voltage while
minimizing the input quiescent current. During Burst
0
0
10
20
30 40
50
60
Mode operation, the LT3434 delivers short bursts of
INPUT VOLTAGE (V)
current to the output capacitor followed by sleep periods
where the output power is delivered to the load by the
Figure 5. I Q vs V IN
3434 F05
output capacitor. In addition, V IN and BIAS quiescent
currents are reduced to typically 45 μ A and 110 μ A respec-
tively during the sleep time. As the load current increases
towards a no load condition, the percentage of time that
the LT3434 operates in sleep mode increases and the
During the sleep portion of the Burst Mode cycle, the V C
pin voltage is held just below the level needed for normal
operation to improve transient response. See the Typical
Performance Characteristics section for burst and tran-
sient response waveforms.
3434fb
15
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