参数资料
型号: LT3506AIDHD#PBF
厂商: Linear Technology
文件页数: 15/24页
文件大小: 0K
描述: IC REG BUCK ADJ 1.6A DL 16DFN
标准包装: 73
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.8 V ~ 22 V
输入电压: 3.6 V ~ 25 V
PWM 型: 电流模式
频率 - 开关: 1.1MHz
电流 - 输出: 1.6A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-WFDFN 裸露焊盘
包装: 管件
供应商设备封装: 16-DFN(5x4)
产品目录页面: 1331 (CN2011-ZH PDF)
LT3506/LT3506A
APPLICATIONS INFORMATION
supply or glitching the input supply when the LT3506 is
enabled. The RUN/SS pins do not provide an accurate
delay to start or an accurately controlled ramp at the
output voltage, both of which depend on the output ca-
pacitance and the load current. However, the power good
indicators can be used to sequence the two outputs, as
described below.
Power Good Indicators
The PG pin is the open collector output of an internal
comparator. PG remains low until the FB pin is within
10% of the ?nal regulation voltage. Tie the PG pin to any
supply with a pull-up resistor that will supply less than
250μA. Note that this pin will be open when the LT3506 is
placed in shutdown mode (both RUN/SS pins at ground)
regardless of the voltage at the FB pin. Power good is valid
when the LT3506 is enabled (either RUN/SS pin is high)
and V IN is greater than ~2.4V.
Output Sequencing
The PG and RUN/SS pins can be used to sequence the
two outputs. Figure 5 shows several circuits to do this. In
each case channel 1 starts ?rst. Note that these circuits
sequence the outputs during start-up. When shut down
the two channels turn off simultaneously. In Figure 5a, a
larger capacitor on RUN/SS2 delays channel 2 with respect
to channel 1. The soft-start capacitor on RUN/SS2 should
be at least twice the value of the capacitor on RUN/SS1.
A larger ratio may be required, depending on the output
capacitance and load on each channel. Make sure to test
the circuit in the system before deciding on ?nal values
for these capacitors. The circuit in Figure 5b requires the
fewest components, with both channels sharing a single
soft-start capacitor. The power good comparator of chan-
nel 1 disables channel 2 until output 1 is in regulation.
For independent control of channel 2, use the circuit in
Figure 5c. The capacitor on RUN/SS1 is smaller than the
RUN/SS1
RUN/SS1
V C2
OFF ON
1nF
LT3506
RUN/SS2
GND
OFF ON
1nF
LT3506
RUN/SS2
GND
PG1
2.2nF
(5a) Channel 2 is Delayed
RUN/SS1
(5b) Fewest Components
RUN/SS1
OFF ON
1nF
LT3506
OFF ON
1nF
LT3506
PG1
RUN/SS2
GND
PG1
RUN/SS2
GND
OFF2 ON2
1.5nF
1.5nF
3506 F05
(5c) Independent Control of Channel 2
(5d) Doesn't Work !
Figure 5. Sequencing the Outputs
3506afc
15
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