参数资料
型号: LT3574IMS#TRPBF
厂商: Linear Technology
文件页数: 14/24页
文件大小: 0K
描述: IC REG FLYBK ISO ADJ .65A 16MSOP
标准包装: 2,500
类型: 回扫,隔离
输出类型: 可调式
输出数: 1
输出电压: 可调至 60V
输入电压: 3 V ~ 40 V
PWM 型: 电流模式,混合
频率 - 开关: 40kHz ~ 1MHz
电流 - 输出: 650mA
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TFSOP(0.118",3.00mm 宽)
包装: 带卷 (TR)
供应商设备封装: 16-MSOP
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LT3574
APPLICATIONS INFORMATION
V IN ( UVLO , RISING ) =
+ 2 . 5 μA ? R 1
V IN ( UVLO , FALLING ) =
SettingtheCurrentLimitResistor
The maximum current limit can be set by placing a resistor
between the R ILIM pin and ground. This provides some
flexibility in picking standard off-the-shelf transformers that
may be rated for less current than the LT3574’s internal
power switch current limit. If the maximum current limit
is needed, use a 10k resistor. For lower current limits, the
following equation sets the approximate current limit:
R ILIM = 65 ? 10 3 ( 0 . 9 A ? I LIM ) + 10 k
The Switch Current Limit vs R ILIM plot in the Typical Per-
formance Characteristics section depicts a more accurate
current limit.
Undervoltage Lockout (UVLO)
The SHDN /UVLO pin is connected to a resistive voltage
divider connected to V IN as shown in Figure 8. The voltage
threshold on the SHDN /UVLO pin for V IN rising is 1.22V.
To introduce hysteresis, the LT3574 draws 2.5μA from the
SHDN /UVLO pin when the pin is below 1.22V. The hysteresis
is therefore user-adjustable and depends on the value of
R1. The UVLO threshold for V IN rising is:
1 . 22 V ? (R1 + R2)
R 2
The UVLO threshold for V IN falling is:
1 . 22 V ? (R1 + R2)
R 2
V IN
SHDN /UVLO
R1
To implement external run/stop control, connect a small
NMOS to the UVLO pin, as shown in Figure 8. Turning the
NMOS on grounds the UVLO pin and prevents the LT3574
from operating, and the part will draw less than a 1μA of
quiescent current.
Minimum Load Requirement
The LT3574 obtains output voltage information through
the transformer while the secondary winding is conducting
current. During this time, the output voltage (multiplied
times the turns ratio) is presented to the primary side of
the transformer. The LT3574 uses this reflected signal to
regulate the output voltage. This means that the LT3574
must turn on every so often to sample the output voltage,
which delivers a small amount of energy to the output.
This sampling places a minimum load requirement on the
output of 1% to 2% of the maximum load.
BIAS Pin Considerations
For applications with an input voltage less than 15V, the
BIAS pin is typically connected directly to the V IN pin. For
input voltages greater than 15V, it is preferred to leave the
BIAS pin separate from the V IN pin. In this condition, the
BIAS pin is regulated with an internal LDO to a voltage of
3V. By keeping the BIAS pin separate from the input voltage
at high input voltages, the physical size of the capacitors
can be minimized (the BIAS pin can then use a 6.3V or
10V rated capacitor).
LT3574
GND
R2
3574 F08
RUN/STOP
CONTROL
(OPTIONAL)
Figure 8. Undervoltage Lockout (UVLO)
3574f
  
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