参数资料
型号: LT3575EFE#PBF
厂商: Linear Technology
文件页数: 15/24页
文件大小: 0K
描述: IC REG FLYBACK ISO ADJ 16TSSOP
标准包装: 95
类型: 回扫,隔离
输出类型: 可调式
输出数: 1
输出电压: 可调至 60V
输入电压: 3 V ~ 40 V
PWM 型: 电流模式,混合
频率 - 开关: 1MHz
电流 - 输出: 2.5A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
供应商设备封装: 16-TSSOP-EP
配用: 732-3306-ND - BOARD EVAL FOR LT3575
相关产品: 732-2669-2-ND - TRANS FLYBACK LT3748 20UH SMD
732-2669-6-ND - TRANS FLYBACK LT3748 20UH SMD
732-2668-6-ND - TRANS FLYBACK LT3748 14UH SMD
732-2667-6-ND - TRANS FLYBACK LT3748 500UH SMD
732-2666-6-ND - TRANS FLYBACK LT3748 12UH SMD
732-2665-6-ND - TRANS FLYBACK LT3748 12UH SMD
732-2664-6-ND - TRANS FLYBACK LT3748 15UH SMD
732-2663-6-ND - TRANS FLYBACK LT3748 15UH SMD
732-2662-6-ND - TRANS FLYBACK LT3748 8UH SMD
732-2661-6-ND - TRANS FLYBACK LT3748 8UH SMD
更多...
LT3575
APPLICATIONS INFORMATION
N =
50 ? V IN ( MAX )
+ V
I OUT ( MAX ) = 0 . 8 ? ( 1 ? D ) ?
NI PK
D =
Minimum Load Requirement
The LT3575 obtains output voltage information through
the transformer while the secondary winding is conducting
current. During this time, the output voltage (multiplied
times the turns ratio) is presented to the primary side of
the transformer. The LT3575 uses this re?ected signal to
regulate the output voltage. This means that the LT3575
must turn on every so often to sample the output voltage,
which delivers a small amount of energy to the output.
This sampling places a minimum load requirement on the
output of 1% to 2% of the maximum load.
A Zener diode with a Zener breakdown of 20% higher
than the output voltage can serve as a minimum load if
pre-loading is not acceptable. For a 5V output, use a 6V
Zener with cathode connected to the output.
BIAS Pin Considerations
For applications with an input voltage less than 15V, the
BIAS pin is typically connected directly to the V IN pin. For
input voltages greater than 15V, it is preferred to leave the
BIAS pin separate from the V IN pin. In this condition, the
BIAS pin is regulated with an internal LDO to a voltage of
3V. By keeping the BIAS pin separate from the input voltage
at high input voltages, the physical size of the capacitors
can be minimized (the BIAS pin can then use a 6.3V or
10V rated capacitor).
Overdriving the BIAS Pin with a Third Winding
The LT3575 provides excellent output voltage regulation
without the need for an optocoupler, or third winding, but
for some applications with higher input voltages (>20V),
it may be desirable to add an additional winding (often
called a third winding) to improve the system ef?ciency.
For proper operation of the LT3575, if a winding is used as
a supply for the BIAS pin, ensure that the BIAS pin voltage
is at least 3.15V and always less than the input voltage.
For a typical 24V IN application, overdriving the BIAS pin
will improve the ef?ciency gain 4-5%.
Loop Compensation
schematics in the Typical Applications section for other
possible values). If too large of an R C value is used, the part
will be more susceptible to high frequency noise and jitter. If
too small of an R C value is used, the transient performance
will suffer. The value choice for C C is somewhat the inverse
of the R C choice: if too small a C C value is used, the loop
may be unstable, and if too large a C C value is used, the
transient performance will also suffer. Transient response
plays an important role for any DC/DC converter.
Design Example
The following example illustrates the converter design
process using LT3575.
Given the input voltage of 20V to 28V, the required output
is 5V, 1A.
V IN(MIN) = 20V, V IN(MAX) = 28V, V OUT = 5V, V F = 0.5V
and I OUT = 1A
1. Select the transformer turns ratio to accommodate
the output.
The output voltage is re?ected to the primary side by a
factor of turns ratio N. The switch voltage stress V SW is
expressed as:
N P
N S
V SW ( MAX ) = V IN + N ( V OUT + V F ) < 50 V
Or rearranged to:
N <
( V OUT F )
On the other hand, the primary side current is multiplied by
the same factor of N. The converter output capability is:
1
2
N ( V OUT + V F )
V IN + N ( V OUT + V F )
The LT3575 is compensated using an external resistor-
capacitor network on the V C pin. Typical values are in
the range of R C = 50k and C C = 1.5nF (see the numerous
3575f
15
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