参数资料
| 型号： | LT3692IUH#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/36页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 3.5A DL 32QFN |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.8 V ~ 34.2 V |
| 输入电压： | 3.6 V ~ 36 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 110kHz ~ 2.5MHz |
| 电流 - 输出： | 3.5A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
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LT3692
PIN FUNCTIONS
SHDN1/2: The shutdown pin is used to control each
channel’s operation. In addition to controlling channel 1,
the SHDN1 pin also activates control circuitry for both
channels and must be present for channel 2 to operate.
When SHDN1 is below its threshold, switching on both
channels is halted. Further reducing the SHDN1 voltage
to 0.6V reduces the quiescent current to a typical value of
6μA. If the shutdown features are not used, the SHDN pin
can be tied to V IN . If SHDN pin is driven by a logic signal,
a series resistor is required. See Applications Information.
SS1/2: Current flowing out the SS pin into an external
capacitor defines the rise time of the output voltage. When
the SS pin is lower than the 0.8V reference, the feedback
is regulated to the SS voltage. When the SS pin exceeds
the reference voltage, the output will regulate the FB pin
voltage to 0.8V and the SS pin will continue to rise until
its clamp voltage. During an output overload, the V C pin is
driven above the maximum switch current level activating
its voltage clamp. When the V C clamp is activated, the SS
pin is discharged until the output reaches a regulation point
that the maximum output current can maintain. When the
overload condition is removed, the output soft starts from
that voltage. In the case of a SHDN or thermal shutdown
event, a power on reset latch ensures the capacitors on
both channels are fully discharged before either is released.
Connecting both SS pins together ensures the outputs
track together.
CLKOUT: The CLKOUT pin generates a square wave of 0V
to 2.5V which is synchronized to the internal oscillator. If
the switching frequency is set by an external resistor the
resultant clock duty cycle will be 50%. If the RT/SYNC pin
is driven by an external clock source, the resultant CLKOUT
duty cycle will mirror the external source.
SW1/2: The SW pin is the emitter of the internal power
NPN. At switch off, the inductor will drive this pin below
ground with a high dV/dt. An external Schottky catch
diode to ground, close to the SW pin and respective V IN
decoupling capacitor’s ground, must be used to prevent
this pin from excessive negative voltages.
T J : The T J pin outputs a voltage proportional to junction
temperature. The pin is 250mV for 25°C and has a slope
of 10mV/°C. See the Applications Information section for
more information.
V C1/2 : The V C pin is the output of the error amplifier and the
input to the peak switch current comparator. It is normally
used for frequency compensation, but can also be used
as a current clamp or control loop override. If the error
amplifier drives V C above the maximum switch current
level, a voltage clamp activates. This indicates that the
output is overloaded and current is pulled from the SS
pin reducing the regulation point.
V IN1 : The V IN1 pin powers the internal control circuitry for
both channels and is monitored by overvoltage/undervolt-
age lockout comparators. The V IN1 pin is also connected
to the collector of channel 1’s on-chip power NPN switch.
The V IN1 pin has high dI/dt edges and must be decoupled
to ground close to the pin of the device.
V IN2 : The V IN2 pin powers the output stage for channel 2
and is monitored by overvoltage/undervoltage lockout
comparators. V IN1 voltage must be greater than 2.8V for
V IN2 operation. The V IN2 pin is also the collector of channel
2’s on-chip power NPN switch. The V IN2 pin has high dI/
dt edges and must be decoupled to ground close to the
pin of the device.
V OUT1/2 : The V OUT pin is the output to the internal sense
resistor that measures current flowing in the inductor.
When the current in the resistor exceeds the current dic-
tated by the V C pin, the SW latch is held in reset disabling
the output switch. Bias current flows out of the V OUT pin.
9
For more information www.linear.com/3692
3692fa
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LT3693 | 制造商:LINER 制造商全称:Linear Technology 功能描述:Monolithic Dual Tracking |
| LT36931DD#PBF | 制造商:Linear Technology 功能描述: |
| LT3693EDD#PBF | 功能描述:IC REG BUCK ADJ 3.5A 10DFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:250 系列:- 类型:降压（降压） 输出类型:固定 输出数:1 输出电压:1.2V 输入电压:2.05 V ~ 6 V PWM 型:电压模式 频率 - 开关:2MHz 电流 - 输出:500mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:6-UFDFN 包装:带卷 (TR) 供应商设备封装:6-SON（1.45x1） 产品目录页面:1032 (CN2011-ZH PDF) 其它名称:296-25628-2 |
| LT3693EDD#TRPBF | 功能描述:IC REG BUCK ADJ 3.5A 10DFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 设计资源:Design Support Tool 标准包装:1 系列:- 类型:升压（升压） 输出类型:固定 输出数:1 输出电压:3V 输入电压:0.75 V ~ 2 V PWM 型:- 频率 - 开关:- 电流 - 输出:100mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SOT-23-5 细型，TSOT-23-5 包装:剪切带 (CT) 供应商设备封装:TSOT-23-5 其它名称:AS1323-BTTT-30CT |
| LT3693EDDPBF | 制造商:Linear Technology 功能描述:DC-DC Converter Step-Down 3.6-36V DFN10 |
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