参数资料
型号: LT3804EFE
厂商: Linear Technology
文件页数: 7/16页
文件大小: 0K
描述: IC REG CTRLR ISO PWM 28-TSSOP
标准包装: 50
PWM 型: 电流/电压模式
输出数: 2
频率 - 最大: 570kHz
占空比: 80%
电源电压: 8 V ~ 25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
包装: 管件
LT3804
OPERATIO
To generate isolated multiple outputs, most systems use
either multiple secondary windings or cascade regulators
for each additional output. Multiple secondary windings
sacrifice regulation of the auxiliary outputs. Cascaded
regulators require a larger inductor for the main output,
because all of the power is processed in series. By gener-
ating the auxiliary output(s) from the secondary winding
of the main output, the LT3804 allows for parallel process-
ing of the output power. This minimizes the main output
inductor size and directly regulates the auxiliary output.
With synchronous rectification, the system efficiency is
greatly improved.
The LT3804 regulates both the main and one auxiliary
output, with true remote sensing to achieve high output
accuracy. To regulate the first output, the LT3804 contains
a high gain error amplifier VA1 and an optocoupler driver
OA1 with a unique feature that reduces output overshoot
to a minimum. For details see the Applications Information
section. The second output includes a voltage amplifier,
VA2, (see Block Diagram)a voltage mode PWM with
trailing edge synchronization and leading edge modula-
tion, a current limit amplifier, CA2, and high speed syn-
chronous switch drivers.
During normal operation (see Figure 2), a switching cycle
begins at the falling edge of the transformer secondary
voltage V S .
The internal oscillator is reset, turning off the top MOSFET,
M1, and turning on the bottom MOSFET, M2. During this
portion of the cycle, the inductor current is discharged by
the output voltage V OUT2 . The transformer secondary
voltage, V S , will go high during this portion of the cycle.
Since M1 is off, the switch node voltage, V SW , remains
zero. The inductor current continues to be discharged by
the output voltage V OUT2 . This condition lasts until the
ramp signal intersects the feedback error amplifier output
V AOUT2 . The top MOSFET M1 turns on, pulling the switch
node voltage to V S . The inductor current of the LT3804
circuit is then charged by V S – V OUT2 . The effective on time
of this buck circuit ends when the secondary voltage
becomes zero. The next cycle repeats. The ideal equation
for duty cycle of the LT3804 is:
D2 = V OUT2 /V SP
where V OUT2 is the auxiliary output voltage, V SP is the
amplitude of the secondary voltage and D2 is the duty
cycle of the switching node voltage V SW , as defined in
Figure 2.
V RESET
T
D 1 T
TRANSFORMER
SECONDARY VOLTAGE
V S
V SP
SYNC SIGNAL V RESET
RAMP V CSET
V AOUT2
TGATE
BGATE
I L2
T
SWITCH NODE V SW
D 2 T
V SP
3710 F02
Figure 2. Leading Edge Modulation, Trailing Edge Synchronization
3804i
7
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