参数资料
型号: LT3804EFE
厂商: Linear Technology
文件页数: 8/16页
文件大小: 0K
描述: IC REG CTRLR ISO PWM 28-TSSOP
标准包装: 50
PWM 型: 电流/电压模式
输出数: 2
频率 - 最大: 570kHz
占空比: 80%
电源电压: 8 V ~ 25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
包装: 管件
LT3804
APPLICATIO S I FOR ATIO
Synchronization and Oscillator Frequency Setting
The switching is synchronized to the secondary winding
falling edge and the synchronization threshold is typically
2.5V. The synchronization falling edge triggers an internal
inverted ramp (see Figure 2) and starts a new switching
cycle for the leading edge voltage mode PWM. The reason
for using leading edge modulation is to leave the trans-
former primary side peak current sensing undisturbed.
For proper synchronization, the oscillator frequency should
be set lower than the system switching frequency with
tolerances taken into account.
f OSC < (f SL ? 0.8)
f SL is the low limit of the system switching frequency and
0.8 is the tolerance of f OSC .
For example, given a system operating at 200kHz with
15% tolerance, then f SL = 200kHz ? 85% = 170kHz; and
f OSC < (170kHz ? 0.8), so f OSC should be set below 136kHz.
Once f OSC is determined, CSET can be calculated by
CSET = (103540pF/f OSC(kHz) ) – 18pF.
For f OSC = 200kHz, CSET = 500pF.
Output Voltage Programming
The LT3804 uses true remote sensing (separate ground
sensing pins, GNDS1 for the first output and GNDS2 for
the second output) to eliminate output error pickup due to
parasitic resistance.
The feedback reference voltages V REF1 and V REF2 are 0.6V
referred to GNDS1 and GNDS2 respectively. The output
voltage can be easily programmed by a resistor divider, as
shown in the Block Diagram:
V OUT1 = 0.6 (1 + R13/R14)
V OUT2 = 0.6 (1 + R3/R4)
For accurate sensing results, GNDS1 and GNDS2 should
stay within –0.1V and 0.1V referred to GND. Note that if
either GNDS1 or GNDS2 is not connected, the LT3804 will
be shut down.
Power Good
When both outputs reach between 90% and 110% of the
programmed level, V PGOOD goes high( a pull-up resistor is
required if the function is used) to signal power good. If
either output rises above 110% or drops below 90%,
V PGOOD goes low after a 200 μ s delay. PGIN1 senses the
first output and PGIN2 senses the second output with a
resistor divider. PGIN1 and PGIN2 are compared to the
references V REF1 and V REF2 respectively. Resistor dividers
should be connected to GNDS1 and GNDS2 with respect
to each output.
Current Limit CA1
The first output current limit is set by the 50mV threshold
across CL1P and CL1N, the inputs of the amplifier CA1. By
connecting an external resistor R S1 (see Block Diagram),
the current limit is set for 50mV/R S1 . C17 on I LCOMP1
stablizes the current limit loop. If current limit is not used,
both CL1P and CL1N should be grounded and C17 is not
needed.
Current Limit CA2
The second output current limit is set by the 50mV
threshold across CL2P and CL2N, the inputs of the ampli-
fier CA2. By connecting an external resistor R S2 (see Block
Diagram), the current limit is set for 50mV/R S2 . R6 and C6
on I LCOMP2 stablize the current limit loop. If current limit
is not used, both CL2P and CL2N should be grounded and
the BGS pin should also be grounded to disable compara-
tor CA2; R6 and C6 are not needed.
where R14 connects to GNDS1 and R4 connects to
GNDS2.
3804i
8
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