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参数资料
| 型号： | LT3844EFE#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 6/24页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST INV PWM 16TSSOP |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 330kHz |
| 占空比： | 95% |
| 电源电压： | 4 V ~ 60 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 是 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 带卷 (TR) |
LT3844
PIN FUNCTIONS
BURST_EN (Pin 4): The BURST_EN pin is used to enable or
disable Burst Mode operation. Connect the BURST_EN pin
to ground to enable the burst mode function. Connect the
pin to V FB or V CC to disable the Burst Mode function.
V FB (Pin 5): The output voltage feedback pin, V FB , is
externally connected to the supply output voltage via a
resistive divider. The V FB pin is internally connected to
the inverting input of the error ampli?er. In regulation,
V FB is 1.231V.
V C (Pin 6): The V C pin is the output of the error ampli?er
whose voltage corresponds to the maximum (peak) switch
current per oscillator cycle. The error ampli?er is typically
con?gured as an integrator circuit by connecting an RC
network from the V C pin to SGND. This circuit creates the
dominant pole for the converter regulation control loop.
Speci?c integrator characteristics can be con?gured to
optimize transient response. When Burst Mode operation
is enabled (see Pin 4 description), an internal low imped-
ance clamp on the V C pin is set at 100mV below the burst
threshold, which limits the negative excursion of the pin
voltage. Therefore, this pin cannot be pulled low with a
low impedance source. If the V C pin must be externally
manipulated, do so through a 1k series resistance.
SYNC (Pin 7): The SYNC pin provides an external clock
input for synchronization of the internal oscillator. R SET
is set such that the internal oscillator frequency is 10%
to 25% below the external clock frequency. If unused the
SYNC pin is connected to SGND. For more information see
“Oscillator Sync” in the Applications Information section
of this data sheet.
f SET (Pin 8): The f SET pin programs the oscillator frequency
with an external resistor, R SET . The resistor is required
even when supplying external sync clock signal. See the
Applications Information section for resistor value selec-
tion details.
SGND (Pin 9, 17): The SGND pin is the low noise ground
reference. It should be connected to the –V OUT side of the
output capacitors. Careful layout of the PCB is necessary
to keep high currents away from this SGND connection.
See the Applications Information section for helpful hints
on PCB layout of grounds.
SENSE – (Pin 10): The SENSE – pin is the negative input for
the current sense ampli?er and is connected to the V OUT
side of the sense resistor for step-down applications. The
sensed inductor current limit is set to 100mV across the
SENSE inputs.
SENSE + (Pin 11): The SENSE + pin is the positive input for
the current sense ampli?er and is connected to the induc-
tor side of the sense resistor for step-down applications.
The sensed inductor current limit is set to 100mV across
the SENSE inputs.
PGND (Pin 12): The PGND pin is the high current ground
reference for internal low side switch and the V CC regulator
circuit. Connect the pin directly to the negative terminal of
the V CC decoupling capacitor. See the Applications Informa-
tion section for helpful hints on PCB layout of grounds.
V CC (Pin 13): The V CC pin is the internal bias supply
decoupling node. Use a low ESR 1μF or greater ceramic
capacitor to decouple this node to PGND. Most internal IC
functions are powered from this bias supply. An external
diode connected from V CC to the BOOST pin charges the
bootstrapped capacitor during the off-time of the main
power switch. Back driving the V CC pin from an external
DC voltage source, such as the V OUT output of the regula-
tor supply, increases overall ef?ciency and reduces power
dissipation in the IC. In shutdown mode this pin sinks
20μA until the pin voltage is discharged to 0V.
SW (Pin 14): In step-down applications the SW pin is
connected to the cathode of an external clamping Schottky
diode, the drain of the power MOSFET and the inductor.
The SW node voltage swing is from V IN during the on-
time of the power MOSFET, to a Schottky voltage drop
below ground during the off-time of the power MOSFET.
In start-up and in operating modes where there is insuf-
?cient inductor current to freewheel the Schottky diode, an
internal switch is turned on to pull the SW pin to ground
so that the BOOST pin capacitor can be charged. Give
careful consideration in choosing the Schottky diode to
limit the negative voltage swing on the SW pin.
TG (Pin 15): The TG pin is the bootstrapped gate drive for
the top N-Channel MOSFET. Since very fast high currents
are driven from this pin, connect it to the gate of the power
MOSFET with a short and wide, typically 0.02" width, PCB
trace to minimize inductance.
3844fb
6
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| LT3844IFE#PBF | 功能描述:IC REG CTRLR BST INV PWM 16TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
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