参数资料
型号: LT4351IMS#PBF
厂商: Linear Technology
文件页数: 12/20页
文件大小: 0K
描述: IC CTLR MOSFET DIODE-OR 10MSOP
标准包装: 50
应用: 并行/冗余电源
FET 型: N 沟道
输出数: 1
内部开关:
延迟时间 - 关闭: 600ns
电源电压: 1.2 V ~ 18 V
电流 - 电源: 1.4mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 管件
产品目录页面: 1338 (CN2011-ZH PDF)
LT4351
APPLICATIONS INFORMATION
C ≥
= 200μF
Asanexample,for500nHofinductanceandR ESR ofabout
100mΩ, then:
4 ? 500nF
0.1 2
Check vendor data for ESR and iterate to get the best
value. Additional C B capacitance may be required for load
concerns.
If the boost regulator is being used, place a 10μF low ESR
ceramic capacitor from V IN to GND. Place a 10μF and a
0.1μF ceramic capacitor close to V IN and GND. These
capacitors should have low ESR (less than 10mΩ for the
10μF and 40mΩ for the 0.1μF). These capacitors help to
eliminate problems associated with noise produced by the
boost regulator. They are decoupled from the V IN supply
by a small 1Ω resistor, as shown in Figure 8. The LT4351
will perform better with a small ceramic capacitor (10μF)
on OUT to GND.
External Boost Supply
The V DD pin may be powered by an external supply. In
this case, simply omit the boost regulator inductor and
diode and leave the SW pin open. Suitable V DD capacitance
(minimum of a 1μF ceramic) should remain due to the
current pulses required for the gate driver.
The V DD current consists of 3.5mA of DC current with the
current required to charge the MOSFET’s gate which is
dependent on the gate charge required and frequency of
switching. Typically the average current will be under 10mA.
L IN
PARASITIC
V IN
MOSFET Selection
The LT4351 uses either a single N-channel MOSFET or
back-to-back N-channel MOSFETs as the pass element.
Back-to-back MOSFETs prevent the MOSFET body diode
from passing current.
Use a single MOSFET if current flow is allowable from
input to output when the input supply is above the output
(limited overvoltage protection). In this case the MOSFET
should have a source on the input side so the body diode
conducts current to the load. Back-to-back MOSFETs are
normally connected with their sources tied together to
provide added protection against exceeding maximum
gate to source voltage.
Selection of MOSFETs should be based on R DS(ON) , BV DSS
and BV GSS . BV DSS should be high enough to prevent
breakdown when V IN or OUT are at their maximum value.
R DS(ON) should be selected to keep within the MOSFET
power rating at the maximum load current (I 2 ? R DS(ON) )
BV GSS should be at least 8V. The LT4351 will clamp the
GATE to 7.5V above the lesser of V IN or OUT. For back-
to-back MOSFETs where sources are tied together, this
allows the use of MOSFETs with a VGS max rating of 8V
or more. If a single MOSFET is used, care must be taken
to ensure the VGS max rating is not exceeded. When the
MOSFET is turned off, the GATE voltage is near ground,
the source at V IN . Thus, MOSFET VGS max must be greater
than V IN(MAX) .
If a single MOSFET is used with source to V IN , then BV GSS
should be greater than the maximum V IN since the MOSFET
gate is at 0.2V when off.
C B
C V3
10μF
1 ?
C V1
10μF
C V2
0.1μF
GATE
V IN
LT4351
GND
4351 F08
Figure 8. V IN Capacitors
4351fd
12
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