- 您现在的位置：买卖IC网 > PDF目录10679 > LT685CN (Linear Technology)IC COMP HI-SPD ECL OUTPUT 16-DIP PDF资料下载
参数资料
| 型号： | LT685CN |
| 厂商： | Linear Technology |
| 文件页数： | 4/8页 |
| 文件大小： | 0K |
| 描述： | IC COMP HI-SPD ECL OUTPUT 16-DIP |
| 标准包装： | 25 |
| 类型： | 带锁销 |
| 元件数： | 1 |
| 输出类型： | 补充型，ECL |
| 电压 - 输入偏移（最小值）： | 2mV @ -5.2V，6V |
| 电流 - 输入偏压（最小值）： | 10µA @ -5.2V，6V |
| 电流 - 输出（标准）： | 30mA |
| 电流 - 静态（最大值）： | 22mA |
| CMRR, PSRR（标准）： | 80dB CMRR |
| 传输延迟（最大）： | 6.5ns |
| 工作温度： | -30°C ~ 85°C |
| 封装/外壳： | 16-DIP（0.300"，7.62mm） |
| 安装类型： | 通孔 |
| 包装： | 管件 |
4
685fa
LT685
LT685C
LT685M
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tPD
Propagation Delay
TA = 25°C
4.5
5.5
6.5
4.5
5.5
6.5
ns
(Note 4)
TA = TMAX
5.0
9.5
5.5
12
ns
TA = TMIN
4.0
6.5
3.5
6.5
ns
tPD(E)
Latch Enable to
TA = 25°C
4.5
5.5
6.5
4.5
5.5
6.5
ns
Output Delay
TA = TMAX
5.0
9.5
5.5
12
ns
(Note 3)
TA = TMIN
4.0
6.5
3.5
6.5
ns
tS
Minimum Set-Up Time
TMIN ≤ TA ≤ 25°C
3.0
ns
(Note 3)
TA = TMAX
4.0
6.0
ns
tH
Minimum Hold Time
TMIN ≤ TA ≤ TMAX
1.0
ns
(Note 3)
tPW(E)
Minimum Latch Enable
TMIN ≤ TA ≤ 25°C
3.0
ns
Pulse Width (Note 3)
TA = TMAX
4.0
5.0
ns
(VIN = 100mV step, 5mV overdrive)
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: For the metal can package, derate at 6.8mW/°C for operation at
ambient temperatures above 100°C; for the hermetic dual-in-line package,
derate at 9mW/°C for operation at ambient temperatures above 105°C.
Note 3: Guaranteed by design, but not tested.
Note 4: Sample tested at 25°C only.
Definitions:
tPD: The propagation delay measured from the time the input signal
crosses the input offset voltage to the 50% point of the output transition.
tPD(E): The propagation delay measured from the 50% point of the latch
enable signal positive transition to the 50% point of the output transition.
tS: The minimum time before the negative transition of the latch enable
signal that an input signal change must be present in order to be acquired
and held at the outputs.
tH: The minimum time after the negative transition of the latch enable
signal that the input signal must remain unchanged in order to be acquired
and held at the outputs.
tPW (E): The minimum time that the latch enable signal must be HIGH in
order to acquire and hold an input signal change.
SWITCHI G CHARACTERISTICS
U
相关PDF资料 |
PDF描述 |
|---|---|
| LTC2499IUHF#PBF | IC ADC 24BIT DELTA SIG 38-QFN |
| ISL41334IRZ-T | TRANSISTOR ESD SGL/DUAL 40-QFN |
| LT1721IS | IC COMP R-RINOUT QUAD 16-SOIC |
| LT1721CGN#TRPBF | IC COMP R-RINOUT QUAD 16-SSOP |
| 85100JC1210PZ50 | CONN RCPT WALL MT 10POS W/PIN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LT685CN#PBF | 功能描述:IC COMP HI-SPD ECL OUTPUT 16-DIP RoHS:是 类别:集成电路 (IC) >> 线性 - 比较器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:通用 元件数:1 输出类型:CMOS，推挽式，满摆幅，TTL 电压 - 电源，单路/双路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 电压 - 输入偏移（最小值）:5mV @ 5.5V 电流 - 输入偏压（最小值）:1pA @ 5.5V 电流 - 输出（标准）:- 电流 - 静态（最大值）:24µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:450ns 磁滞:±3mV 工作温度:-40°C ~ 85°C 封装/外壳:6-WFBGA，CSPBGA 安装类型:表面贴装 包装:管件 其它名称:Q3554586 |
| LT685M | 制造商:LINER 制造商全称:Linear Technology 功能描述:High Speed Comparator |
| LT685MH | 制造商:LINER 制造商全称:Linear Technology 功能描述:High Speed Comparator |
| LT685MH/883 | 制造商:Linear Technology 功能描述:High speed comparator |
| LT685MJ | 制造商:Linear Technology 功能描述:Comparator Single ±7V 16-Pin CDIP |
发布紧急采购，3分钟左右您将得到回复。