参数资料
| 型号： | LT8500IUHH#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 4/24页 |
| 文件大小： | 0K |
| 描述： | IC PWM GENERATOR 56-QFN |
| 标准包装： | 2,500 |
| 类型： | PWM 发生器 |
| PLL： | 无 |
| 主要目的： | LED 照明 |
| 输入： | CMOS，TTL |
| 输出： | CMOS，TTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 0.075 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 50MHz |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-WFQFN 裸露焊盘 |
| 供应商设备封装： | 56-QFN-EP（5x9） |
| 包装： | 带卷 (TR) |
LT8500
12
8500f
these two signals between chips. When properly balanced
in this way, the SCKO/SDO timing will meet the timing
requirements of SCKI/SDI on the next cascaded chip,
enabling faster clock speeds and more chips in cascade.
The host controller sends the SDI signal with the SCKI
signal, and receives the SDO signal with the SCKO signal.
The controller will see skew between SCKI and SCKO,
and will need to operate on two clock planes depending
on the number of cascaded LT8500s and system timing
constraints. A duty cycle change (tDC-SCK ) will also occur
between SCKI and SCKO, limiting the number of LT8500s
in a chain, depending on SCKI speed. This change results
from a slight difference in propagation delays of the posi-
tive and negative edges of SCKI. LDIBLANK skew between
chips may require balancing in timing critical systems,
otherwise the host should increase the delay between
SCKI and LDI to avoid violating LDI to SCKI setup and
hold times (tSU-LDI and tHD-LDI). In summary, the 5-wire
topology extends the maximum number of cascadable
chips, boosts the series data interface clock frequency,
eliminates global SCKI routing, reduces the need of buf-
fer insertion for SCKI signals, and offers an easier PCB
layout. In a low-speed application with a small number of
cascaded chips, the 5-wire topology can be simplified to
the 4-wire topology by ignoring the SCKO output.
In a 4-wire topology, the LDIBLANK and SCKI signals
need global routing while the SDI signal only needs local
routing between chips. SCKO is ignored. When a large
number of chips are in cascade, or long board traces
are used, external clock-tree buffers with corresponding
driving capability might be needed for the LDIBLANK and
SCKI signals to minimize signal skews. The propagation
delay caused by the buffer insertion on the SCKI signal
yields the skew between the SCKI and SDI signals, which
usually requires balancing. Since both the SDI and SDO
signals require the same SCKI signal to send and receive,
the propagation delay between the SDI and SDO signals
limits the number of chips in cascade and the series data
interface clock frequency.
Communication
Figure 3 shows two command frames sent on SDI, and
one status frame received on SDO. All the frames have
the same 584-bit length and are transmitted with the most
significant channel first, and each field is transmitted with
MSB first. The command frames are sent with the SCKI
signal and the status frame is received with the SCKO
signal. The command field determines the function of a
frame, according to Table 2. The status frame consists of
the four MSB’s of the last command (CR[7:4]), the open
LED self test bit (OLT), the synchronization error status
bit (SYC), the phase-shift status bit (PHS), the correction
register disable status bit (CRD), and individual OPENLED
fault bits (NOL[48:1]), as well as each 6-bit correction
register (COR[48:1]). Logic zeros fill in the unused bits
of the status frame. Refer to Figure 3.
Figure 4 illustrates the timing relationship among serial
input and serial output signals in more detail. One correc-
tion register frame followed by an update frame is sent
through the SDI, SCKI, and LDIBLANK pins. At the same
time, two status frames are received through the SDO,
SCKO, and LDIBLANK pins. The rising edges of SCKI shift
a frame of data into shift register SR[0:583]. After 584
clock cycles, all bits of data sit in the shift register waiting
for the LDI signal. An asynchronous LDIBLANK “high”
signal captures the decoded 8-bit CMD field (CR[7:0]),
executing commands and routing data accordingly. At
the same time, a frame of status information, including
the 4 MSB’s of the CMD field (CR[7:4]), status bits, COR
registers, and individual open LED fault flags, is parallel
loaded into the 584-bit shift register and will be shifted
out as the next frame shifts in.
LDIBLANK = LDI + BLANK
The LDIBLANK pin is a dual function input, determined by
the duration of a logic high on the pin. LDI is the latch data
input, which signals the end of a frame and executes the
command in the CMD field (CR[7:0]). The BLANK signal
turns off the PWM[48:1] outputs and performs a global
reset of the part, including the shift register in the serial
interface. A logic high on LDIBLANK always asserts LDI,
while a logic high greater than the minimum LDIBLANK
pulsedurationforBLANK(tWH-BLANK)alsoassertsBLANK.
BLANKwillneverbeassertedifthepinisheldhighlessthan
the maximum LDIBLANK pulse duration for LDI (tWH-LDI).
Between maximum tWH-LDI and minimum tWH-BLANK,
BLANK becomes asserted at an undetermined time.
operaTion
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